cuda-fanout: drop legacy demo_ops references — bend-cuda only
Earlier rename kept DEMO_OPS env fallback + *binary-demo-ops* var name as transitional back-compat. With both hosts redeployed on bend-cuda that's no longer needed. Renamed: *binary-demo-ops* -> *binary-bend-cuda* DEMO_OPS env -> removed (only BEND_CUDA recognized now) Also bulk-updated cuda-fanout sibling docs (DESIGN, CATALOG, plans/) that still spelled the old name. Slot reserved for future bend-rocm / bend-cpu via parallel env vars.
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5 changed files with 15 additions and 16 deletions
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@ -20,7 +20,7 @@ form-status column says `planned` until numbers exist.
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| form | binary | hardware | speedup vs CPU | wire shape |
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|-----------------------|-------------------------|----------|-------------------------------|-------------------------------------------------------------|
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| `cuda-shake-fanout` | `shake256-fanout` | 3090 | 12x over host hashlib at 1M x 16 B inputs | `(cuda-shake-fanout (quote (hex …)) out-bytes)` + BSHK binary |
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| `cuda-sim-ops-bin` | `ecdsa/cuda/demo_ops` | 3090 | 1.27x at 141 batches (9024 shots); crossover ~115 batches; **SHAKE-RNG mode** matches upstream Pareto: Σ Toffoli = 15,999,651,264 & avg Toffoli = 1,773,011.000 bit-identical to `eval_circuit` on same `ops.bin` | `(cuda-sim-ops-bin "path/to/ops.bin" n-batches)` — `demo_ops` defaults `--rng-mode shake` (Fiat-Shamir over op stream, matches upstream); `--rng-mode lfsr` keeps legacy xorshift for debug parity |
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| `cuda-sim-ops-bin` | `ecdsa/cuda/bend-cuda` | 3090 | 1.27x at 141 batches (9024 shots); crossover ~115 batches; **SHAKE-RNG mode** matches upstream Pareto: Σ Toffoli = 15,999,651,264 & avg Toffoli = 1,773,011.000 bit-identical to `eval_circuit` on same `ops.bin` | `(cuda-sim-ops-bin "path/to/ops.bin" n-batches)` — `bend-cuda` defaults `--rng-mode shake` (Fiat-Shamir over op stream, matches upstream); `--rng-mode lfsr` keeps legacy xorshift for debug parity |
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| `cuda-bignum-cgbn` | `cgbn-batch-worker` | 3090 | 1.28 Gops/s kernel mod-mul at n=1M (256-bit, ~256x GMP CPU); 9 ops total | `BCGB` binary: op_id + bitwidth + n + modulus + a + b |
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| `cuda-secp256k1-batched-mul`| `secp256k1-batch-mul` | 3090 | v1 7.86 Mkeys/s @ n=1M; v3 (windowed-G w=4) **13.83 Mkeys/s @ n=1M** (1.76x v1; ~309x coincurve); Day-4 v4 (v3 ladder + Montgomery batch inv) regressed -12% vs v3 due to v2 serial-per-block walks; warp-scan Phase B/D refactor needed before v4 wins; daemon default flipped to `--window-w 4` | `BSCP` binary: scalars + base-point |
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| `cuda-sim-axis-flip` | `ecdsa/cuda/demo_axis` | 3090 | 217 Mops/s @ K=32 M=4 (per-candidate parallel); 23.7x over per-shot N=4 at same M; LOSES to per-shot by 14% at full N=128 saturation | `(cuda-sim-axis (variant-paths …) n-shots)` |
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@ -31,7 +31,7 @@ form-status column says `planned` until numbers exist.
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conditional-op heavy & branch-divergent. This catalog exists so
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we DO NOT pretend 1.27x is the ceiling — we find forms with real
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SIMT-friendly shape & route work through them. **As of
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2026-06-06 our SHAKE-RNG mode anchors `demo_ops` measurements
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2026-06-06 our SHAKE-RNG mode anchors `bend-cuda` measurements
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directly against upstream's public Pareto scoreboard** — Σ Toffoli
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& avg Toffoli are byte-identical to `eval_circuit` on the same
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`ops.bin`, no calibration constant required.
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@ -17,7 +17,7 @@ In www.foxhop.net's `ecdsa/cuda/`:
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| binary | purpose | upstream byte-parity? |
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|--------|---------|----------------------|
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| `demo` | hand-crafted 21-op circuit, CPU↔GPU smoke | n/a |
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| `demo_ops` | ops.bin loader, LFSR RNG, scoring | gate counts ✓ |
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| `bend-cuda` | ops.bin loader, LFSR RNG, scoring | gate counts ✓ |
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| `demo_upstream` | SHAKE + secp256k1 register init | full (every digit) |
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| `demo_multi` | multi-candidate batch driver, S-exp portal output | per candidate |
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@ -47,7 +47,7 @@ Add a `cuda-sim-ops-bin` op (analogous to today's `cuda-shake-fanout`):
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(n-batches (car (cdr args)))
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(portal-out (gensym-path "/tmp/bend-cuda-sim" ".portal"))
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(cmd (string-append
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"/home/fox/git/www.foxhop.net/ecdsa/cuda/demo_ops "
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"/home/fox/git/www.foxhop.net/ecdsa/cuda/bend-cuda "
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ops-path
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" --batches " (number->string n-batches)
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" --portal " portal-out)))
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@ -79,7 +79,7 @@ With bend:
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(define (eval-variant-cuda variant-id ops-bin-path)
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(let* ((result (bend!-call
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(list 'cuda-sim-ops-bin ops-bin-path 141))))
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;; result shape from demo_ops's portal:
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;; result shape from bend-cuda's portal:
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;; (cuda-multi-result (ops-path …) (status OK)
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;; (totals (clifford N) (toffoli N))
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;; (timing-ms …))
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@ -91,7 +91,7 @@ With bend:
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Each variant emits its own `ops.bin` (the upstream binary format we
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parse with `ops_loader.c`), the search loop bends it to a GPU worker,
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worker calls `demo_ops`, returns the portal, lumbda picks the
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worker calls `bend-cuda`, returns the portal, lumbda picks the
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winner.
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## What's missing before this lands
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@ -114,7 +114,7 @@ winner.
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in lumbda's in-process `sim.lsp`; large ones bend to GPU.
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- Wire protocol identical to `cuda-shake-fanout` — no new primitive
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beyond a Scheme registration entry.
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- `demo_ops --portal` output already matches lumbda's S-expression
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- `bend-cuda --portal` output already matches lumbda's S-expression
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ingestion contract (see `ecdsa/cuda/main_ops.c` portal writer).
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- Worker pool elasticity: any GPU host can register
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`cuda-sim-ops-bin` and become eligible to receive candidate
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@ -38,11 +38,10 @@
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;; bend-cuda lives in the foxhop ecdsa repo and runs upstream-format
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;; ops.bin against the CPU+GPU simulators, writing (cuda-sim-result …)
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;; portals via --portal. No daemon mode: spawn-per-call.
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;; BEND_CUDA env override > legacy DEMO_OPS env > default bend-cuda path
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;; > legacy demo_ops symlink (still in place during the rename transition).
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(define *binary-demo-ops*
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;; BEND_CUDA env override > default bend-cuda path. AMD ROCm path
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;; will land as BEND_ROCM env / bend-rocm binary; CPU fallback BEND_CPU.
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(define *binary-bend-cuda*
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(or (get-environment-variable "BEND_CUDA")
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(get-environment-variable "DEMO_OPS")
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"/home/fox/git/www.foxhop.net/ecdsa/cuda/bend-cuda"))
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;; cgbn-batch-worker — bend form B. CGBN bignum batch over BSHK protocol;
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@ -265,7 +264,7 @@
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(let* ((argv (list ops-path
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(number->string n-batches)
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"--portal" portal-path))
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(pair (spawn-process-stdio *binary-demo-ops* argv)))
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(pair (spawn-process-stdio *binary-bend-cuda* argv)))
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;; bend-cuda does not read stdin; drain stdout until exit.
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(drain-to-eof (cdr pair))
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(close-port (car pair))
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@ -134,7 +134,7 @@ make demo_axis NVCC=/usr/bin/nvcc ARCH=sm_86
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--shots 4 --force-mem --portal /tmp/axis-K32-M4.portal
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# baseline per-shot comparison at same total lanes
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./demo_ops /tmp/ops.bin 128
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./bend-cuda /tmp/ops.bin 128
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```
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Portal format `(cuda-axis-result ...)` — lumbda search loops ingest
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@ -83,7 +83,7 @@ Three options surfaced in our brief; you pick **(b)**:
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Phase B point-add Toffoli fraction (from existing kernel counters):
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roughly half of all gates per circuit are CCX / CCZ at current ancilla
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widths. Confirm exact ratio by running `demo_ops` against
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widths. Confirm exact ratio by running `bend-cuda` against
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`point-add.bin` — GPU counters at `sim_gpu.cu:238-239` emit
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`cliff_out` & `toff_out` per batch. Record this ratio before you sink
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time into Form D: if Toffoli > 90% of ops, a Clifford-only sim
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@ -203,7 +203,7 @@ Two axes:
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- **Per-candidate axis flip benchmark.** Run N independent candidate
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circuits as N GPU blocks (= N lanes). Compare:
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- existing `demo_ops` per-shot: N candidates × 8192 shots each = 8192N
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- existing `bend-cuda` per-shot: N candidates × 8192 shots each = 8192N
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threads, one thread per shot of a single candidate;
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- new `demo_stab_sim_ops` per-candidate: N candidates × 1 lane each,
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each lane runs its candidate to completion serially in tableau.
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@ -240,7 +240,7 @@ For one experienced CUDA + quantum-sim engineer (assumes prior
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Aaronson-Gottesman familiarity):
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- Day 1: read STABSim PDF, read Aaronson-Gottesman paper, run
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existing `demo_ops` to measure Toffoli ratio, decide go/no-go.
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existing `bend-cuda` to measure Toffoli ratio, decide go/no-go.
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- Days 2-4: `stab_sim_gpu.cu` kernel — tableau rep, X/Z/H/S/CX/M
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update rules, warp-level row-XOR primitive.
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- Day 5: `main_stab_sim.c` daemon loop, BSHK plumbing.
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