From e57c4948ab626143d51ba1080f25085176024af0 Mon Sep 17 00:00:00 2001 From: "russell@unturf.com" Date: Tue, 9 Jun 2026 15:17:04 -0400 Subject: [PATCH] =?UTF-8?q?cuda-fanout:=20drop=20legacy=20demo=5Fops=20ref?= =?UTF-8?q?erences=20=E2=80=94=20bend-cuda=20only?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Earlier rename kept DEMO_OPS env fallback + *binary-demo-ops* var name as transitional back-compat. With both hosts redeployed on bend-cuda that's no longer needed. Renamed: *binary-demo-ops* -> *binary-bend-cuda* DEMO_OPS env -> removed (only BEND_CUDA recognized now) Also bulk-updated cuda-fanout sibling docs (DESIGN, CATALOG, plans/) that still spelled the old name. Slot reserved for future bend-rocm / bend-cpu via parallel env vars. --- examples/cuda-fanout/CATALOG.md | 4 ++-- examples/cuda-fanout/DESIGN-ecdsa-integration.md | 10 +++++----- examples/cuda-fanout/gpu-worker.lsp | 9 ++++----- examples/cuda-fanout/plans/form-D-axis-flip-RESULTS.md | 2 +- .../cuda-fanout/plans/form-D-clifford-stabilizer.md | 6 +++--- 5 files changed, 15 insertions(+), 16 deletions(-) diff --git a/examples/cuda-fanout/CATALOG.md b/examples/cuda-fanout/CATALOG.md index e479081..9c00133 100644 --- a/examples/cuda-fanout/CATALOG.md +++ b/examples/cuda-fanout/CATALOG.md @@ -20,7 +20,7 @@ form-status column says `planned` until numbers exist. | form | binary | hardware | speedup vs CPU | wire shape | |-----------------------|-------------------------|----------|-------------------------------|-------------------------------------------------------------| | `cuda-shake-fanout` | `shake256-fanout` | 3090 | 12x over host hashlib at 1M x 16 B inputs | `(cuda-shake-fanout (quote (hex …)) out-bytes)` + BSHK binary | -| `cuda-sim-ops-bin` | `ecdsa/cuda/demo_ops` | 3090 | 1.27x at 141 batches (9024 shots); crossover ~115 batches; **SHAKE-RNG mode** matches upstream Pareto: Σ Toffoli = 15,999,651,264 & avg Toffoli = 1,773,011.000 bit-identical to `eval_circuit` on same `ops.bin` | `(cuda-sim-ops-bin "path/to/ops.bin" n-batches)` — `demo_ops` defaults `--rng-mode shake` (Fiat-Shamir over op stream, matches upstream); `--rng-mode lfsr` keeps legacy xorshift for debug parity | +| `cuda-sim-ops-bin` | `ecdsa/cuda/bend-cuda` | 3090 | 1.27x at 141 batches (9024 shots); crossover ~115 batches; **SHAKE-RNG mode** matches upstream Pareto: Σ Toffoli = 15,999,651,264 & avg Toffoli = 1,773,011.000 bit-identical to `eval_circuit` on same `ops.bin` | `(cuda-sim-ops-bin "path/to/ops.bin" n-batches)` — `bend-cuda` defaults `--rng-mode shake` (Fiat-Shamir over op stream, matches upstream); `--rng-mode lfsr` keeps legacy xorshift for debug parity | | `cuda-bignum-cgbn` | `cgbn-batch-worker` | 3090 | 1.28 Gops/s kernel mod-mul at n=1M (256-bit, ~256x GMP CPU); 9 ops total | `BCGB` binary: op_id + bitwidth + n + modulus + a + b | | `cuda-secp256k1-batched-mul`| `secp256k1-batch-mul` | 3090 | v1 7.86 Mkeys/s @ n=1M; v3 (windowed-G w=4) **13.83 Mkeys/s @ n=1M** (1.76x v1; ~309x coincurve); Day-4 v4 (v3 ladder + Montgomery batch inv) regressed -12% vs v3 due to v2 serial-per-block walks; warp-scan Phase B/D refactor needed before v4 wins; daemon default flipped to `--window-w 4` | `BSCP` binary: scalars + base-point | | `cuda-sim-axis-flip` | `ecdsa/cuda/demo_axis` | 3090 | 217 Mops/s @ K=32 M=4 (per-candidate parallel); 23.7x over per-shot N=4 at same M; LOSES to per-shot by 14% at full N=128 saturation | `(cuda-sim-axis (variant-paths …) n-shots)` | @@ -31,7 +31,7 @@ form-status column says `planned` until numbers exist. conditional-op heavy & branch-divergent. This catalog exists so we DO NOT pretend 1.27x is the ceiling — we find forms with real SIMT-friendly shape & route work through them. **As of -2026-06-06 our SHAKE-RNG mode anchors `demo_ops` measurements +2026-06-06 our SHAKE-RNG mode anchors `bend-cuda` measurements directly against upstream's public Pareto scoreboard** — Σ Toffoli & avg Toffoli are byte-identical to `eval_circuit` on the same `ops.bin`, no calibration constant required. diff --git a/examples/cuda-fanout/DESIGN-ecdsa-integration.md b/examples/cuda-fanout/DESIGN-ecdsa-integration.md index 5b4433c..e3fb45f 100644 --- a/examples/cuda-fanout/DESIGN-ecdsa-integration.md +++ b/examples/cuda-fanout/DESIGN-ecdsa-integration.md @@ -17,7 +17,7 @@ In www.foxhop.net's `ecdsa/cuda/`: | binary | purpose | upstream byte-parity? | |--------|---------|----------------------| | `demo` | hand-crafted 21-op circuit, CPU↔GPU smoke | n/a | -| `demo_ops` | ops.bin loader, LFSR RNG, scoring | gate counts ✓ | +| `bend-cuda` | ops.bin loader, LFSR RNG, scoring | gate counts ✓ | | `demo_upstream` | SHAKE + secp256k1 register init | full (every digit) | | `demo_multi` | multi-candidate batch driver, S-exp portal output | per candidate | @@ -47,7 +47,7 @@ Add a `cuda-sim-ops-bin` op (analogous to today's `cuda-shake-fanout`): (n-batches (car (cdr args))) (portal-out (gensym-path "/tmp/bend-cuda-sim" ".portal")) (cmd (string-append - "/home/fox/git/www.foxhop.net/ecdsa/cuda/demo_ops " + "/home/fox/git/www.foxhop.net/ecdsa/cuda/bend-cuda " ops-path " --batches " (number->string n-batches) " --portal " portal-out))) @@ -79,7 +79,7 @@ With bend: (define (eval-variant-cuda variant-id ops-bin-path) (let* ((result (bend!-call (list 'cuda-sim-ops-bin ops-bin-path 141)))) - ;; result shape from demo_ops's portal: + ;; result shape from bend-cuda's portal: ;; (cuda-multi-result (ops-path …) (status OK) ;; (totals (clifford N) (toffoli N)) ;; (timing-ms …)) @@ -91,7 +91,7 @@ With bend: Each variant emits its own `ops.bin` (the upstream binary format we parse with `ops_loader.c`), the search loop bends it to a GPU worker, -worker calls `demo_ops`, returns the portal, lumbda picks the +worker calls `bend-cuda`, returns the portal, lumbda picks the winner. ## What's missing before this lands @@ -114,7 +114,7 @@ winner. in lumbda's in-process `sim.lsp`; large ones bend to GPU. - Wire protocol identical to `cuda-shake-fanout` — no new primitive beyond a Scheme registration entry. -- `demo_ops --portal` output already matches lumbda's S-expression +- `bend-cuda --portal` output already matches lumbda's S-expression ingestion contract (see `ecdsa/cuda/main_ops.c` portal writer). - Worker pool elasticity: any GPU host can register `cuda-sim-ops-bin` and become eligible to receive candidate diff --git a/examples/cuda-fanout/gpu-worker.lsp b/examples/cuda-fanout/gpu-worker.lsp index 2dfa5db..2b03a66 100644 --- a/examples/cuda-fanout/gpu-worker.lsp +++ b/examples/cuda-fanout/gpu-worker.lsp @@ -38,11 +38,10 @@ ;; bend-cuda lives in the foxhop ecdsa repo and runs upstream-format ;; ops.bin against the CPU+GPU simulators, writing (cuda-sim-result …) ;; portals via --portal. No daemon mode: spawn-per-call. -;; BEND_CUDA env override > legacy DEMO_OPS env > default bend-cuda path -;; > legacy demo_ops symlink (still in place during the rename transition). -(define *binary-demo-ops* +;; BEND_CUDA env override > default bend-cuda path. AMD ROCm path +;; will land as BEND_ROCM env / bend-rocm binary; CPU fallback BEND_CPU. +(define *binary-bend-cuda* (or (get-environment-variable "BEND_CUDA") - (get-environment-variable "DEMO_OPS") "/home/fox/git/www.foxhop.net/ecdsa/cuda/bend-cuda")) ;; cgbn-batch-worker — bend form B. CGBN bignum batch over BSHK protocol; @@ -265,7 +264,7 @@ (let* ((argv (list ops-path (number->string n-batches) "--portal" portal-path)) - (pair (spawn-process-stdio *binary-demo-ops* argv))) + (pair (spawn-process-stdio *binary-bend-cuda* argv))) ;; bend-cuda does not read stdin; drain stdout until exit. (drain-to-eof (cdr pair)) (close-port (car pair)) diff --git a/examples/cuda-fanout/plans/form-D-axis-flip-RESULTS.md b/examples/cuda-fanout/plans/form-D-axis-flip-RESULTS.md index 9415620..e610b8c 100644 --- a/examples/cuda-fanout/plans/form-D-axis-flip-RESULTS.md +++ b/examples/cuda-fanout/plans/form-D-axis-flip-RESULTS.md @@ -134,7 +134,7 @@ make demo_axis NVCC=/usr/bin/nvcc ARCH=sm_86 --shots 4 --force-mem --portal /tmp/axis-K32-M4.portal # baseline per-shot comparison at same total lanes -./demo_ops /tmp/ops.bin 128 +./bend-cuda /tmp/ops.bin 128 ``` Portal format `(cuda-axis-result ...)` — lumbda search loops ingest diff --git a/examples/cuda-fanout/plans/form-D-clifford-stabilizer.md b/examples/cuda-fanout/plans/form-D-clifford-stabilizer.md index 1d3239f..3b40c6f 100644 --- a/examples/cuda-fanout/plans/form-D-clifford-stabilizer.md +++ b/examples/cuda-fanout/plans/form-D-clifford-stabilizer.md @@ -83,7 +83,7 @@ Three options surfaced in our brief; you pick **(b)**: Phase B point-add Toffoli fraction (from existing kernel counters): roughly half of all gates per circuit are CCX / CCZ at current ancilla -widths. Confirm exact ratio by running `demo_ops` against +widths. Confirm exact ratio by running `bend-cuda` against `point-add.bin` — GPU counters at `sim_gpu.cu:238-239` emit `cliff_out` & `toff_out` per batch. Record this ratio before you sink time into Form D: if Toffoli > 90% of ops, a Clifford-only sim @@ -203,7 +203,7 @@ Two axes: - **Per-candidate axis flip benchmark.** Run N independent candidate circuits as N GPU blocks (= N lanes). Compare: - - existing `demo_ops` per-shot: N candidates × 8192 shots each = 8192N + - existing `bend-cuda` per-shot: N candidates × 8192 shots each = 8192N threads, one thread per shot of a single candidate; - new `demo_stab_sim_ops` per-candidate: N candidates × 1 lane each, each lane runs its candidate to completion serially in tableau. @@ -240,7 +240,7 @@ For one experienced CUDA + quantum-sim engineer (assumes prior Aaronson-Gottesman familiarity): - Day 1: read STABSim PDF, read Aaronson-Gottesman paper, run - existing `demo_ops` to measure Toffoli ratio, decide go/no-go. + existing `bend-cuda` to measure Toffoli ratio, decide go/no-go. - Days 2-4: `stab_sim_gpu.cu` kernel — tableau rep, X/Z/H/S/CX/M update rules, warp-level row-XOR primitive. - Day 5: `main_stab_sim.c` daemon loop, BSHK plumbing.