catalog + bend.html: cuda-sim-ops-bin row gains SHAKE-RNG anchor note
demo_ops in foxhop ecdsa repo now defaults --rng-mode shake (Fiat-Shamir over op stream, ports eval_circuit::fiat_shamir_seed verbatim). Σ Toffoli & avg Toffoli on stock ops.bin match upstream eval_circuit bit-for-bit: 15,999,651,264 / 1,773,011.000 across 141 batches (9024 shots) on a 3090. Our cuda-sim-ops-bin numbers now compare directly to upstream's public Pareto scoreboard with no calibration constant. Catalog row & bend.html row updated to document the shake/lfsr toggle & the upstream-match guarantee. Throughput figure also refreshed to 1.27x at 141 batches (from prior 1.07x at 128 batches).
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@ -134,8 +134,8 @@ make gpu-worker LUMBDA=asm # smallest footprint</code></pre>
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<tr>
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<td><code>cuda-sim-ops-bin</code></td>
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<td>RTX 3090</td>
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<td>1.07× at 128 batches; crossover ~115 batches</td>
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<td><code>(cuda-sim-ops-bin "path/to/ops.bin" n-batches)</code></td>
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<td>1.27× at 141 batches (9024 shots); crossover ~115 batches; <strong>SHAKE-RNG mode</strong> matches upstream Pareto bit-for-bit (Σ Toffoli = 15,999,651,264, avg Toffoli = 1,773,011.000 on stock <code>ops.bin</code>)</td>
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<td><code>(cuda-sim-ops-bin "path/to/ops.bin" n-batches)</code> — <code>demo_ops</code> defaults <code>--rng-mode shake</code> (Fiat-Shamir over op stream); <code>--rng-mode lfsr</code> keeps legacy xorshift for debug parity</td>
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</tr>
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<tr>
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<td><code>cuda-sim-axis-flip</code></td>
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