From a4613b685ecf1185871a920500618b9c7dfd7268 Mon Sep 17 00:00:00 2001 From: "russell@unturf.com" Date: Fri, 5 Jun 2026 21:26:20 -0400 Subject: [PATCH] bend.html: rewrite back to focused doc shape MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Page had accreted session debugging (Form D structural finding, opt 1/opt 3 narrative, Day-4 v4 regression notes, robustness fix narrative, first measured sweep paragraphs). Stripped all of it. What stays: - what bend is - start a worker - call it - wire protocol (S-exp vs binary modes + measured table) - fleet (2-host cluster table + brief coexistence note + cluster aggregate numbers) - catalog: live forms (5) + Wave 1 (A-G detailed) + Wave 2 + 3 (compact tables) + why-a-form-earns-its-slot criteria - source pointers What goes (back to CATALOG.md / plan docs where they belong): - Form D structural finding paragraph - Form D opt 1 + opt 3 RESULTS narrative - Day-4 v4 regression detail in the secp row - First measured ECDSA-mission sweep paragraphs - Robustness gap fix paragraph Page length: 371 → ~226 lines. Reads as a reference doc again instead of a session log. --- www/bend.html | 289 +++++++++++++++----------------------------------- 1 file changed, 87 insertions(+), 202 deletions(-) diff --git a/www/bend.html b/www/bend.html index 01bb7d3..fc2a9bd 100644 --- a/www/bend.html +++ b/www/bend.html @@ -22,9 +22,6 @@

bend is a Lumbda primitive that decides per call whether to evaluate locally or ship to a CUDA worker over our wire protocol. Tiny inputs stay local; heavy inputs bend to a worker that holds a warm CUDA context across requests. The decision uses a cost estimator on the argument shape, not the operation name.

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-This page documents the protocol, the wire numbers we measured, and a catalog of forms — standalone CUDA binaries with published speedups that bend can dispatch to. -

@@ -53,12 +50,11 @@ make gpu-worker LUMBDA=asm # smallest footprint ;; Heavy — cost above threshold, ships to the GPU worker (bend (cuda-shake-fanout one-million-inputs 32)) -

On a single RTX 3090 with a warm daemon, SHAKE256 fan-out matched hashlib.shake_256 byte-for-byte and won by 1.5–10× across the workloads we measured. Below the break-even (~100 MB of bulk hash work) host CPU stays faster — the cost estimator picks correctly.

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Wire protocol — two modes

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The CUDA kernel runs inside the leaf binary; what the tier choice affects is wire orchestration. The wire has two modes: S-expression text (the default — hex strings inside a Scheme list) and binary (magic BSHK header + raw bytes, identical layout to the daemon's binary portal). Binary mode bypasses S-expression parsing entirely:

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Wire protocol

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Two modes: S-expression text (the default) and binary (magic BSHK header + raw bytes). Binary mode bypasses S-expression parsing entirely.

@@ -69,285 +65,174 @@ make gpu-worker LUMBDA=asm # smallest footprint
workloadPy S-expPy binaryC S-expC binary
1M × 16 B23,811 ms159 msCLIFF157 ms
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Binary mode wins by 30–200× over S-expression mode at scale. At 1 M × 16 B inputs, C tier binary is 157 ms end-to-end versus 23,811 ms for the S-exp path — a 150× speedup. The CUDA kernel itself on this 3090 runs in ~47 ms; binary wire adds ~110 ms of file I/O + framing on top, a 2.5× multiplier instead of the 500× multiplier the S-exp path imposed.

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Critically, at huge workloads bend now beats host hashlib: host SHAKE256 over 1 M tiny inputs is ~2 s on a single Python core; bend via binary worker is 157 ms — a 12× speedup of host. The cost estimator in bend.lsp should be updated to know about the binary path so the routing decision picks GPU at this scale instead of staying local.

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Binary mode lives behind the BSHK magic byte in the wire payload. S-expression callers see no change; binary callers prepend the magic and send raw bytes. See examples/cuda-fanout/bench_tiers.py --binary for the protocol implementation.

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Three tiers, three operating points (S-expression mode): C tier wins at small & medium scales (8× faster than Python); asm tier hits 0.21 ms at very small inputs (~30% behind C, 6× faster than Python, 70 KB statically linked, zero libc); Python tier scales linearly (~22 µs per input) all the way through 1 M inputs but runs slowly on a single core. The S-exp CLIFFs at 10k (C) and 1k (asm) are tier-internal reader limits — binary mode bypasses them entirely.

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The CUDA toolchain stays isolated to the leaf binary the worker spawns. No tier links libcudart; no tier requires nvcc at build time. Asm tier hosts workers through hand-written pipe2 + fork + execve syscalls — no libc anywhere on the chain.

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Real workload — ecdsafail search

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Beyond hash fan-out, bend now dispatches quantum-reversible circuit scoring for a secp256k1 point-addition challenge attack (research artifact, internal repo). Lumbda emits an upstream-format ops.bin from a Phase B Roetteler 12-step circuit, calls (bend!-call '(cuda-sim-ops-bin path 141)), & receives Σ Clifford / Σ Toffoli totals back from a GPU worker over our binary wire — same cross-tier validation, same byte-identical portal contract the hash demo proves. Search loops on any host tier ship candidate scoring to whichever fleet node holds a warm CUDA context.

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Measured on a 3090 against HEAD's 12.8 M-op kickmix ops.bin (716 MB):

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n_batchesshotswire-scpu-msgpu-msgpu/cpu
1645.5425,1070.008
161,0247.38505,8000.146
644,09611.43,4446,2160.553
1288,19217.17,0606,6041.07
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Crossover at ~115 batches. GPU kernel carries ~5,070 ms of fixed overhead (init + alloc + upload) plus ~12 ms per batch; CPU runs ~55 ms per batch. The kickmix circuit's conditional ops cause branch divergence — this is one form where GPU does not dominate. Honest numbers go in the catalog below.

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Binary mode wins by 30–200× over S-expression mode at scale. At 1 M × 16 B inputs, C tier binary is 157 ms end-to-end versus 23,811 ms for the S-exp path. At that scale bend beats host hashlib by ~12×.

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The CUDA toolchain stays isolated to the leaf binary the worker spawns. No tier links libcudart; no tier requires nvcc at build time. Asm tier hosts workers through hand-written pipe2 + fork + execve syscalls.

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Fleet — cross-GPU & cluster numbers

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bend runs on a 2-host LAN cluster today. The worker on each box is a lumbda C-tier process; daemons stay warm across requests. Round-robin selection lives in bend.lsp via *bend-workers* & the BEND_WORKERS environment variable.

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Fleet

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bend runs on a 2-host LAN cluster. Round-robin selection lives in bend.lsp via *bend-workers* & the BEND_WORKERS environment variable.

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hostGPUarchportdaemons livecoexists with
hostGPUarchportcoexists with
3090-ai.foxhop.netRTX 3090 (24 GB)sm_869091shake / cgbn / secp / sim-ops-bin / sim-axis-flipidle
ai.foxhop.netRTX 4090 (24 GB)sm_899092shake / cgbn / secpqwen LLM on GPU
3090-ai.foxhop.netRTX 3090 (24 GB)sm_869091idle
ai.foxhop.netRTX 4090 (24 GB)sm_899092qwen LLM (llama.cpp) on GPU
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The 4090 box shares the GPU with a qwen LLM (llama.cpp). Our bend kernels fit alongside qwen comfortably because the secp256k1 / CGBN workloads burn the SMs only for milliseconds at a time, then release. The qwen server keeps its model weights resident; our kernels allocate transient VRAM for the per-call batch, run, free, return. 24 GB VRAM is enough for both.

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Cross-GPU parity at small batches

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Single-call kernel time at n=100k CGBN 256-bit mod-mul:

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hostkernel mswall ms (incl. PCIe + wire)Mops/s (wall)
3090-ai0.07–0.10336 (median)0.30
ai (4090)0.07–0.10362 (median)0.28
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At n=100k, kernels finish faster than the per-call PCIe transfer (6.4 MB tx) + LAN wire round trip. Both GPUs run the same workload in the same kernel time because neither saturates — both starve between calls. The 4090's raw FLOPS advantage shows up only when the kernel runs long enough to amortize wire overhead.

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Cluster aggregate — round-robin fan-out

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workloadsolo (1 host)cluster (2 hosts)speedup
200 × n=1k CGBN mod-mul0.052 Mops/s0.084 Mops/s1.6×
6 × n=100k CGBN mod-mul0.15 Mops/s0.18 Mops/s1.2×
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Speedup caps at 1.6× instead of 2× because the dispatching client serializes one call at a time. An async fan-out client unlocks the remaining 2× headroom. Workers themselves never block each other.

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First measured ECDSA-mission sweep

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The first end-to-end run through the full lumbda → emit-ops-bin walker → bend → demo_ops pipeline landed today at runs/lumbda-sweep-001/. Two of six lever variants emitted & scored at p=11 point-add width:

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variantn_opsΣ CliffordΣ Toffoli
Solinas + Fermat textbook B-Y48,7631,687,232749,056
Solinas + refined B-Y (Phase B step 10)32,3331,237,440475,648
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Refined Bernstein-Yang cuts Σ Toffoli by 36.5% at production-relevant width. Our small-fixture lever screen predicted −56% at p=5, & the p=251 ground-truth reference predicted −40%. Measured −36.5% sits within 3 percentage points of the larger-width prediction. The small-fixture lever screen earns its keep as a faithful predictor: sweep cheap at p=11, filter to winners, promote only winners to p=251 production cost.

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Four remaining variants still emitting (the lumbda walker is CPU-bound on the local box at full Phase B width); dispatch-sweep.py auto-resumes against new .bin files as they land.

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Robustness

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The binary handlers (handle-binary-shake, handle-binary-cgbn, handle-binary-secp) used to call delete-file unconditionally after daemon failure — if the daemon errored before writing the output portal, the missing-file raise crashed the entire listener. 12 guard lines across 6 sites ((if (file-exists? PATH) (delete-file PATH))) closed the gap. Fix held under sustained sweep traffic with zero crashes since deployment.

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The 4090 box shares its GPU with a qwen LLM. Bend kernels fit alongside because secp256k1 / CGBN workloads burn SMs for milliseconds at a time then release; qwen keeps its weights resident, bend allocates transient VRAM per call. 24 GB VRAM holds both.

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Cluster aggregate (round-robin fan-out, sequential dispatcher): 1.6× at 200 × n=1k CGBN mod-mul, 1.2× at 6 × n=100k. Cap is client-side serialization; an async dispatcher unlocks the remaining 2× headroom. Workers themselves never block each other.

Form catalog

A form earns a slot here only after we have published a benchmark or measured one on our hardware. "I think this would be fast" does not earn a slot — the form-status column says planned until numbers exist.

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Form D structural finding — 2026-06-05

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cuda-clifford-stabilizer as originally scoped does not apply to our point-add circuit. Build agent measured Toffoli fraction 13.87% (well under the 40% threshold), then noticed the circuit contains no Hadamard or S gates — only X / CX / CCX / CZ / CCZ / SWAP / R / HMR / Z / NEG. State never leaves the computational basis. Aaronson-Gottesman tableau compression buys nothing when superposition does not exist; it reduces to exactly what sim_gpu.cu already does, at one bit per qubit per shot.

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The cuda-sim-ops-bin 1.07× ceiling traces to memory-bandwidth on per-shot striped state, not algorithm choice. STABSim-class wins remain valid for QEC / surface-code workloads where H + S exist; that's a future workload, not point-add today.

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Both replacement directions landed 2026-06-05; the bandwidth-bound diagnosis they were chasing turned out FALSE for our circuit.

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Both pivots converged on the same diagnosis: the 3090 is compute-saturated at ~250 Mops/s on the kickmix circuit, not bandwidth-saturated. Real next macro-lever: multi-GPU fan-out across our fleet.

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Status legend

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The catalog grows continuously. Each form below carries enough metadata for anyone to start a port: canonical reference, reported speedup, target hardware, sketch wire shape. Forms with HIGH relevance to our active missions (foxhop ECDSA work, undefect defect-scanning, unsandbox / unturf permacomputer infrastructure) move up the build queue.

Live forms

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formstatushardwarespeedup vs CPUwire shape
formhardwarethroughputwire shape
cuda-shake-fanoutlive RTX 309012× over host hashlib at 1 M × 16 B inputs(cuda-shake-fanout '(hex ...) out-bytes) + BSHK binary12× host hashlib at 1 M × 16 B inputs(cuda-shake-fanout '(hex ...) out-bytes) + BSHK binary
cuda-sim-ops-binlive RTX 30901.07× at 128 batches (8192 shots); crossover ~115 batches1.07× at 128 batches; crossover ~115 batches (cuda-sim-ops-bin "path/to/ops.bin" n-batches)
cuda-bignum-cgbnlivecuda-sim-axis-flip RTX 30901.28 Gops/s kernel mod-mul at n=1M (256-bit, ~256× GMP single-thread CPU); all 9 ops live (mod-add/sub/mul/sqr/inv/exp/reduce, add-no-mod, mul-no-mod-2x-width)217 Mops/s @ K=32 M=4 (many-candidates × few-shots)(cuda-sim-axis (variant-paths ...) n-shots)
cuda-bignum-cgbnRTX 30901.28 Gops/s kernel mod-mul @ n=1M (256-bit, ~256× GMP CPU); 9 ops BCGB binary: op_id + bitwidth + n + modulus + a + b
cuda-secp256k1-batched-mullive RTX 3090v1 7.86 Mkeys/s @ n=1M; v3 (windowed-G w=4) 13.83 Mkeys/s @ n=1M — 1.76× v1, ~309× coincurve CPU. Day-4 v4 (v3 ladder + Montgomery batch inv) regressed -12% vs v3 due to v2's serial-per-block Phase B/D walks; warp-scan Phase B/D refactor needed before v4 wins. Daemon default now ships --window-w 413.83 Mkeys/s @ n=1M (~309× coincurve CPU; windowed-G ladder w=4) BSCP binary: scalars + base-point → BSCR points
cuda-sim-axis-flipliveRTX 3090217 Mops/s @ K=32 M=4 per-candidate-parallel kickmix sim; 23.7× over per-shot N=4 at same M; loses to per-shot by 14% at full N=128 saturation. Right tool for lumbda search-loop early-screen many-candidates × few-shots pattern(cuda-sim-axis (variant-paths ...) n-shots)
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Surveyed forms (published precedent, build queued)

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Surveyed forms (Wave 1)

A. cuda-secp256k1-batched-mul — batched secp256k1 scalar / point ops

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Speedup: gECC 4.94× on unknown-point mul, 5.56× on ECDSA verify vs CPU. VanitySearch forks hit 6.5 Gkeys/s on RTX 4090, 8.6 Gkeys/s on RTX 5090, 2.65 Gkeys/s on RTX 3080. Endomorphism + Montgomery batch-inversion (one mod-inv per N points instead of N) carries the kernel.

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Reference numbers: gECC 4.94× on unknown-point mul, 5.56× on ECDSA verify vs CPU. VanitySearch forks hit 6.5 Gkeys/s on RTX 4090, 8.6 Gkeys/s on RTX 5090, 2.65 Gkeys/s on RTX 3080.

Wire: (secp-mul-batch (scalars . blob<N×32B>) (base-point . blob<64B>)) → (points . blob<N×64B>)

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References: gECC paper · VanitySearch · VanitySearch-Bitcrack fork

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Refs: gECC paper · VanitySearch · VanitySearch-Bitcrack

B. cuda-bignum-cgbn — 256-bit modular arithmetic primitives

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Speedup: 100×+ on dense mul vs Xeon-20c + GMP + OpenMP on V100 (midsize-int study).

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Reference numbers: 100×+ on dense mul vs Xeon-20c + GMP + OpenMP on V100.

Wire: (cgbn-batch (op . mod-mul|mod-inv|mod-add) (modulus . blob<32B>) (a . blob<N×32B>) (b . blob<N×32B>)) → blob<N×32B>

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References: NVlabs CGBN · midsize-int benchmarks

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Refs: NVlabs CGBN · midsize-int benchmarks

C. cuda-rho-pollard-walk — Pollard rho / kangaroo walks

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Speedup: 87.7 M ops/sec on RTX 2070 Super for ECCp79 (Certicom challenge solved in ~3 hours). Original CUDA Pollard paper reports > 7.2 M points/sec at 256 threads on older HW.

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Reference numbers: 87.7 M ops/sec on RTX 2070 Super for ECCp79. Original CUDA Pollard paper reports > 7.2 M points/sec at 256 threads on older hardware.

Wire: (rho-walk-batch (start-points . blob<W×64B>) (steps . N) (distinguished-mask . blob<32B>)) → (distinguished . blob<K×96B>)

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References: atlomak/CUDA-rho-pollard · oritwoen/kangaroo

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Refs: atlomak/CUDA-rho-pollard · oritwoen/kangaroo

D. cuda-clifford-stabilizer — tableau stabilizer simulator (Stim-on-GPU)

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Speedup: 186× over Stim (CPU SOTA) on equivalence-checking. STABSim a first GPU stabilizer sim to scale better than CPU on QEC workloads.

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Reference numbers: 186× over Stim (CPU SOTA) on equivalence-checking.

Wire: (stab-sim-batch (n-qubits . k) (circuit . blob) (n-shots . S)) → (samples . blob<S×ceil(k/8)>)

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References: STABSim · Qimax · equivalence-checking

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Refs: STABSim · Qimax · equivalence-checking

E. cuda-bernstein-yang-inv — batched modular inverse (safegcd)

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Speedup: 3–10× per inversion over Fermat on CPU. No published dedicated CUDA implementation found — gECC uses Montgomery's batched-inversion trick instead. Standalone Bernstein-Yang-on-CUDA holds novel territory.

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Reference numbers: 3–10× per inversion over Fermat on CPU. No published dedicated CUDA implementation; Standalone Bernstein-Yang-on-CUDA holds novel territory.

Wire: (modinv-batch (modulus . blob<32B>) (xs . blob<N×32B>)) → blob<N×32B>

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References: safegcd · Jumping for Bernstein-Yang

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Refs: safegcd · Jumping for Bernstein-Yang

F. cuda-ntt-poly — Number Theoretic Transform

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Speedup: Up to 123× over CPU; 21× on RTX 3070; cuFFT-comparable kernel structure.

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Reference numbers: Up to 123× over CPU; 21× on RTX 3070; cuFFT-comparable kernel structure.

Wire: (ntt (mod . p) (omega . root) (xs . blob<N×8B>)) → blob<N×8B>

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References: NTTSuite · FHE NTT

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Refs: NTTSuite · FHE NTT

G. cuda-radix-sort / cuda-prefix-scan — reduction primitives

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Speedup: 1.4 G keys/sec on Titan; 20–50× over CPU merge sort; 257× over Intel Xeon Phi for scan.

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Reference numbers: 1.4 G keys/sec on Titan; 20–50× over CPU merge sort; 257× over Intel Xeon Phi for scan.

Wire: (sort-u64 (xs . blob<N×8B>)) → blob<N×8B>

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References: NVIDIA CUB · Onesweep

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Refs: NVIDIA CUB · Onesweep

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Wave 2 — broader surveyed forms (2026-06-05)

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Sorted by reported speedup vs CPU descending. Speedups quoted from published benchmarks on the cited hardware; numbers labelled surveyed have not yet run on our fleet, so this table calls a paper a paper and a measurement a measurement.

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Surveyed forms (Wave 2)

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Sorted by reported speedup descending.

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formspeeduphardwarerelevanceref
formthroughputhardwareref
cuda-minhash-weighted600–1000× vs numpy+MKLTitan X vs 12-core Xeon E5-1650HIGH — undefect corpus dedup, CVE shard clusteringsrc-d/minhashcuda
cuda-cuckoo-filter378× insert, 258× deleteA100 (TCF on Perlmutter)HIGH — foxhop ECDSA candidate-pruning, undefect URL-seen filterarXiv:2603.15486
cuda-aes-ctr-chacha20211–400 GB/s (ChaCha8 / ChaCha20)single GPU (RTX 3070 sustaining 672 Gbps Poly1305)HIGH — AEAD on lumbda portal envelopes between tiersAsyncGBP
cuda-suffix-array-skew30–242× vs CPU SA-ISTesla K20MEDIUM — substring search for undefect source-corpus scansLiu/Luo
cuda-kdtree-build30–242× build, 1.6–200× kNNRTX (RT cores)MEDIUM — spatial index for unsandbox fleet localityZhou et al.
cuda-sat-paraFROST-elim93× peak, 48× avg on variable elimNVIDIA + CADICAL/Kissat baselineHIGH — ECDSA / reversible-circuit equivalence checking via CNFParaFROST
cuda-aho-corasick-pfac~50–100× (IDS pkt-inspect)GTX-classHIGH — secret/CVE-string scan across OSS source mirrorsPFAC
cuda-dilithium-pqsig57.7× keygen+sign+verify vs single CPU threadRTX 3090 TiHIGH — PQ migration for unsandbox TLS, foxhop disclosure signingIACR 2024/1365
cuda-mc-options-pricing25–152× (barrier-call kernel 152×)Tesla C1060 / modernLOW — calibration form, well-understood arithmeticGPU Gems Ch.45
cuda-cuFFT-batched-1D8–32× vs MKL; tcFFT 1.1–3.2× vs cuFFTV100 / A100MEDIUM — spectrogram dispatch for punters-cc audio correlationtcFFT
cuda-blake3-tree~5–20× (tree mode)Blaze-3 CUDAHIGH — content-addressed lumbda portal frames, foxhop attachmentsBlaze-3
cuda-bloom-filter-modern~6× CPU; 3.4 B inserts/sB200 / PerlmutterHIGH — foxhop candidate-pruning, undefect scan-target known-setarXiv:2512.15595
cuda-gemm-batched-FP84.8× FP8 vs A100; 716 TFLOPS H100H100 SXMLOW — calibration form, lattice-PQC matrix substratecuBLAS 12.0
cuda-batched-matrix-inverse4.3–16.8× vs MAGMAP100 (650–800 GF SP)LOW — linear-algebra verifiers on reversible-circuit checkingSuperfri 2018
cuda-hash-join-radix4 B tuples/s single; 1.8 T tuples/s on 1024 A100A100 clusterMEDIUM — undefect CVE↔commit↔package joinsADMS-21
cuda-kmer-count4–6× vs KMC2; ~2× Jellyfish/KMC1RapidGKC, GerbilLOW — bioinformatics adjacency; identical bend-portal shapeRapidGKC
cuda-cgraph-traversal38 B TEPS; PageRank half-billion nodes in secondsDGX2MEDIUM — undefect dependency-DAG analytics, upstream call-graphscuGraph
cuda-triangle-count-TRUST~1 T TEPS (first trillion-TEPS triangle counter)multi-A100MEDIUM — community-structure detection for twitter-x-puntersTRUST
cuda-ldpc-bp-decoder10 Gbps with early-terminationGPGPULOW — PQ-KEM noise modelling, SDR experiments on radio nodesMDPI Electronics 2022
cuda-nvcomp-zstd2.2× decompress (zstd); 1.4× LZ4; 1.9× snappyH100 / A100HIGH — undefect corpus shards, lumbda portal envelopes, permacomputer ingestnvCOMP
cuda-minhash-weighted600–1000× vs numpy+MKLTitan X vs Xeon E5-1650src-d/minhashcuda
cuda-cuckoo-filter378× insert, 258× deleteA100arXiv:2603.15486
cuda-aes-ctr-chacha20211–400 GB/ssingle GPUAsyncGBP
cuda-suffix-array-skew30–242× vs CPU SA-ISTesla K20Liu/Luo
cuda-kdtree-build30–242× build, 1.6–200× kNNRTX (RT cores)Zhou et al.
cuda-sat-paraFROST-elim93× peak, 48× avg variable elimNVIDIA + Kissat baselineParaFROST
cuda-aho-corasick-pfac~50–100× IDS pkt-inspectGTX-classPFAC
cuda-dilithium-pqsig57.7× keygen+sign+verify vs single CPU threadRTX 3090 TiIACR 2024/1365
cuda-mc-options-pricing25–152×Tesla C1060 / modernGPU Gems Ch.45
cuda-cuFFT-batched-1D8–32× vs MKL; tcFFT 1.1–3.2× vs cuFFTV100 / A100tcFFT
cuda-blake3-tree~5–20× tree modeBlaze-3 CUDABlaze-3
cuda-bloom-filter-modern~6× CPU; 3.4 B inserts/sB200 / PerlmutterarXiv:2512.15595
cuda-gemm-batched-FP84.8× FP8 vs A100; 716 TFLOPS H100H100 SXMcuBLAS 12.0
cuda-batched-matrix-inverse4.3–16.8× vs MAGMAP100Superfri 2018
cuda-hash-join-radix4 B tuples/s single; 1.8 T tuples/s on 1024 A100A100 clusterADMS-21
cuda-kmer-count4–6× vs KMC2RapidGKC, GerbilRapidGKC
cuda-cgraph-traversal38 B TEPSDGX2cuGraph
cuda-triangle-count-TRUST~1 T TEPSmulti-A100TRUST
cuda-ldpc-bp-decoder10 Gbps with early-terminationGPGPUMDPI Electronics 2022
cuda-nvcomp-zstd2.2× zstd; 1.4× LZ4; 1.9× snappyH100 / A100nvCOMP
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Wave 3 — surveyed 2026-06-05

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15 additional forms spanning ZK / SNARK provers, pairing crypto, tensor network contraction, sparse linear algebra, CV primitives, numerical solvers, generic belief propagation, MD/CFD kernels, convex optimization, DSP beyond cuFFT, DB aggregations, graph theory beyond triangle/PageRank. Sorted by reported speedup or absolute throughput descending.

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Surveyed forms (Wave 3)

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formspeedup / throughputhardwarerelevanceref
formthroughputhardwareref
cuda-fluidx3d-lbm100–200× vs ANSYS Fluent / OpenFOAM; 8,799 MLUPS single A100A100unsandbox MEDIUM (HPC reproducibility, OpenCL backend matches our fleet)FluidX3D
cuda-mfcc-spectral~97× CPU MFCC; STFT ~75× via cuSignal vs SciPyGTX 580 / RTX 30-seriesunsandbox HIGH — punters-cc, BT-DISC forensics, real-time CC pipelinecuSignal
cuda-batched-lp-simplex95× over CPLEX; 5× over GLPK on a batch of 100K LPsGTX 980-classunsandbox HIGH — resource scheduling, Prime Mission workstation balancingarXiv 1802.08557
cuda-betweenness-centrality-weighted30–150× warp-centric weighted BCGTX onwardsundefect HIGH — workaholic-node detection on dependency DAG, directly matches MOAD-0001 modelarXiv 1701.05975
cuda-cudasift-orb-ransac~60× SIFT CPU→GPU (11 fps 1920×1440); 1.2 ms on GTX 1060; ORB 11.3×GTX 1060+unsandbox MEDIUM (visual evidence pipeline for incident reports)CudaSift
cuda-cudasw-gasal2CUDASW++4.0 16.2× over v3.0; 134× over ADEPT; 5.71 TCUPS on H100; GASAL2 packing 750× vs NVBioH100 (TCUPS)undefect MEDIUM (binary-diff & patch-similarity at scale: SW reduces to opcode-sequence diff)CUDASW++4.0
cuda-loopy-bp-mrf45× over CPU LBP for stereo MRF inferenceGTX 280-class+undefect HIGH — LBP substrate for FuzzingBrain-style probabilistic program analysisarXiv 2509.22337
cuda-sgm-stereo42 fps at 640×480 with 128 disparities on Tegra X1; 46 fps on discrete GPUsTegra X1 / discreteunsandbox MEDIUM (embedded ARM+CUDA matches our edge node profile)arXiv 1610.04121
cuda-hungarian-lap10–50× class; 400 M-variable LAP in ~13 sNVIDIA GPUunsandbox HIGH — workstation-to-queue balancing per Prime Mission; defect-cluster ↔ patch-bundle assignment for undefectScienceDirect
cuda-msm-bls12-38127.86× over Pippenger (RELIC) AVX baseline; 60% of Groth16 prover time on single GPUA100 / RTX 4090ECDSA HIGH — Pippenger bucket sort + multi-G1 arithmetic shares branchless modmul shape with our reversible secp256k1 inner loopSimdMSM TCHES
cuda-pdwt-lifting15.9× over best optimized CPU DWT (lifting scheme)GTX / Teslaunsandbox MEDIUM (audio-IPC payload analysis, BT signal denoising)PDWT
cuda-tensornet-contract8–20× vs CuPy on contraction; tensor QR ~100× vs Xeon 8480+; tensor SVD ~10×A100ECDSA HIGH — alternative to stabilizer/kickmix sim path; MPS/PEPS evaluates reversible secp256k1 circuits beyond CliffordcuTensorNet
cuda-ega-gpu-aggregation6.45–29.12× over CPU multi-pass EGA; group-by hash 19.4×NVIDIA GPUundefect HIGH — defect-corpus aggregation at planetary scale; unsandbox HIGH — telemetry queue aggregationVLDB Top-k EGA
cuda-bicgstab-ilu-spmvSpTRSV 10.7×; ILU0 BiCGSTAB 3.2× vs cuSPARSE on MI210; GMRES(30) block-ISAI 1.4–6.9×V100 / MI210ECDSA MEDIUM (sparse LA over GF(p) underpins lattice / index-calc); undefect MEDIUM (spectral analysis on DAG)arXiv 2508.04917
cuda-icicle-snark-groth16ICICLE-Snark fastest Groth16 today; Mina GPU 3× over libsnark; NTT 91% of prover at large sizesRTX 4090 / A100ECDSA MEDIUM (zk + MSM stack shares finite-field discipline); undefect MEDIUM (zk-prover defect scanning)ICICLE-Snark
cuda-fluidx3d-lbm100–200× vs ANSYS Fluent; 8,799 MLUPS single A100A100FluidX3D
cuda-mfcc-spectral~97× CPU MFCC; STFT ~75× via cuSignalGTX 580 / RTX 30-seriescuSignal
cuda-batched-lp-simplex95× over CPLEX; 5× over GLPKGTX 980-classarXiv 1802.08557
cuda-betweenness-centrality-weighted30–150× warp-centric weighted BCGTX onwardsarXiv 1701.05975
cuda-cudasift-orb-ransac~60× SIFT CPU→GPU; ORB 11.3×GTX 1060+CudaSift
cuda-cudasw-gasal2CUDASW++4.0 16.2×; 5.71 TCUPS on H100H100CUDASW++4.0
cuda-loopy-bp-mrf45× over CPU LBP for stereo MRFGTX 280+arXiv 2509.22337
cuda-sgm-stereo42 fps @ 640×480, 128 disparitiesTegra X1 / discretearXiv 1610.04121
cuda-hungarian-lap10–50×; 400 M-variable LAP in ~13 sNVIDIA GPUScienceDirect
cuda-msm-bls12-38127.86× over Pippenger AVX baselineA100 / RTX 4090SimdMSM TCHES
cuda-pdwt-lifting15.9× over best optimized CPU DWTGTX / TeslaPDWT
cuda-tensornet-contract8–20× vs CuPy; tensor QR ~100× vs XeonA100cuTensorNet
cuda-ega-gpu-aggregation6.45–29.12× multi-pass; group-by 19.4×NVIDIA GPUVLDB Top-k EGA
cuda-bicgstab-ilu-spmvSpTRSV 10.7×; BiCGSTAB 3.2× vs cuSPARSEV100 / MI210arXiv 2508.04917
cuda-icicle-snark-groth16fastest Groth16 today; NTT 91% of proverRTX 4090 / A100ICICLE-Snark
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Wave 3 filter-outs: AMGX algebraic multigrid (2–5×), GROMACS GPU (2–3×), NVOFA optical flow (7–10× borderline, dedicated hardware unit), Junction-tree BP per-message (0.68–9.18×), batched L-BFGS (134× single-case, not generalized). All below 10× or insufficiently general; revisit when shape changes.

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Skipped — revisit when shape changes

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Why a form earns its slot

A form is GPU-worth-it when at least one of:

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  1. Embarrassingly parallel. N independent items, no cross-item dependency. SHAKE fan-out, batched mod-mul, bulk point-add — each thread owns one item.
    2. -
  2. Dense, branch-free inner loop. Same operation on every element. Matrix-vector, convolution, bit-twiddling sweeps.
    3. -
  3. Reduction-friendly. Tree-reduce / prefix-sum / parallel-scan patterns GPU hardware accelerates natively.
    4. -
  4. Big batch amortizes fixed kernel overhead. Our cuda-sim-ops-bin shows ~5 s kernel overhead; only worth it past ~115 batches.
    5. +
  5. Embarrassingly parallel. N independent items, no cross-item dependency.
    6. +
  6. Dense, branch-free inner loop. Same operation on every element.
    7. +
  7. Reduction-friendly. Tree-reduce / prefix-sum / parallel-scan patterns.
    8. +
  8. Big batch amortizes fixed kernel overhead.
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When none of these hold, do not force the problem onto GPU. Find a different decomposition: parallelize on a different axis (per-candidate instead of per-shot), or stay on CPU & fan out across fleet hosts.

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Recommended build order

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    -
  1. A — cuda-secp256k1-batched-mul: biggest immediate win. VanitySearch's CUDA secp256k1 kernel hits 6.5 Gkeys/s on a 4090; bend gets a GPU-rate point-mul oracle for candidate validation.
    2. -
  2. D — cuda-clifford-stabilizer: the right axis fix for our 1.07× cuda-sim-ops-bin ceiling. Reshape circuit-sim per-candidate-parallel; targets a Clifford fragment via STABSim-style tableau.
    3. -
  3. B — cuda-bignum-cgbn: foundational layer. Generic 256-bit vocabulary lumbda calls without committing to a curve.
    4. -
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Forms E, C, G follow once A–D give us measured numbers on our hardware. F & below revisit when our shape changes.

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When none of these hold, find a different decomposition: parallelize on a different axis, or stay on CPU & fan out across fleet hosts.

Source & specs

-examples/cuda-fanout/ — wire contract, daemon protocol, bench data, per-tier integration sketch.
-CATALOG.md — canonical source for form metadata; this page renders from the same data. +examples/cuda-fanout/ — wire contract, daemon protocol, bench data, per-tier integration.
+CATALOG.md — canonical source for form metadata.