bend is a Lumbda primitive that decides per call whether to evaluate locally or ship to a CUDA worker over our wire protocol. Tiny inputs stay local; heavy inputs bend to a worker that holds a warm CUDA context across requests. The decision uses a cost estimator on the argument shape, not the operation name.
-This page documents the protocol, the wire numbers we measured, and a catalog of forms — standalone CUDA binaries with published speedups that bend can dispatch to. -
On a single RTX 3090 with a warm daemon, SHAKE256 fan-out matched hashlib.shake_256 byte-for-byte and won by 1.5–10× across the workloads we measured. Below the break-even (~100 MB of bulk hash work) host CPU stays faster — the cost estimator picks correctly.
The CUDA kernel runs inside the leaf binary; what the tier choice affects is wire orchestration. The wire has two modes: S-expression text (the default — hex strings inside a Scheme list) and binary (magic BSHK header + raw bytes, identical layout to the daemon's binary portal). Binary mode bypasses S-expression parsing entirely:
Two modes: S-expression text (the default) and binary (magic BSHK header + raw bytes). Binary mode bypasses S-expression parsing entirely.
| workload | Py S-exp | Py binary | C S-exp | C binary |
|---|---|---|---|---|
| 1M × 16 B | 23,811 ms | 159 ms | CLIFF | 157 ms |
Binary mode wins by 30–200× over S-expression mode at scale. At 1 M × 16 B inputs, C tier binary is 157 ms end-to-end versus 23,811 ms for the S-exp path — a 150× speedup. The CUDA kernel itself on this 3090 runs in ~47 ms; binary wire adds ~110 ms of file I/O + framing on top, a 2.5× multiplier instead of the 500× multiplier the S-exp path imposed.
-Critically, at huge workloads bend now beats host hashlib: host SHAKE256 over 1 M tiny inputs is ~2 s on a single Python core; bend via binary worker is 157 ms — a 12× speedup of host. The cost estimator in bend.lsp should be updated to know about the binary path so the routing decision picks GPU at this scale instead of staying local.
Binary mode lives behind the BSHK magic byte in the wire payload. S-expression callers see no change; binary callers prepend the magic and send raw bytes. See examples/cuda-fanout/bench_tiers.py --binary for the protocol implementation.
Three tiers, three operating points (S-expression mode): C tier wins at small & medium scales (8× faster than Python); asm tier hits 0.21 ms at very small inputs (~30% behind C, 6× faster than Python, 70 KB statically linked, zero libc); Python tier scales linearly (~22 µs per input) all the way through 1 M inputs but runs slowly on a single core. The S-exp CLIFFs at 10k (C) and 1k (asm) are tier-internal reader limits — binary mode bypasses them entirely.
-The CUDA toolchain stays isolated to the leaf binary the worker spawns. No tier links libcudart; no tier requires nvcc at build time. Asm tier hosts workers through hand-written pipe2 + fork + execve syscalls — no libc anywhere on the chain.
Beyond hash fan-out, bend now dispatches quantum-reversible circuit scoring for a secp256k1 point-addition challenge attack (research artifact, internal repo). Lumbda emits an upstream-format ops.bin from a Phase B Roetteler 12-step circuit, calls (bend!-call '(cuda-sim-ops-bin path 141)), & receives Σ Clifford / Σ Toffoli totals back from a GPU worker over our binary wire — same cross-tier validation, same byte-identical portal contract the hash demo proves. Search loops on any host tier ship candidate scoring to whichever fleet node holds a warm CUDA context.
Measured on a 3090 against HEAD's 12.8 M-op kickmix ops.bin (716 MB):
| n_batches | shots | wire-s | cpu-ms | gpu-ms | gpu/cpu |
|---|---|---|---|---|---|
| 1 | 64 | 5.5 | 42 | 5,107 | 0.008 |
| 16 | 1,024 | 7.3 | 850 | 5,800 | 0.146 |
| 64 | 4,096 | 11.4 | 3,444 | 6,216 | 0.553 |
| 128 | 8,192 | 17.1 | 7,060 | 6,604 | 1.07 |
Crossover at ~115 batches. GPU kernel carries ~5,070 ms of fixed overhead (init + alloc + upload) plus ~12 ms per batch; CPU runs ~55 ms per batch. The kickmix circuit's conditional ops cause branch divergence — this is one form where GPU does not dominate. Honest numbers go in the catalog below.
+Binary mode wins by 30–200× over S-expression mode at scale. At 1 M × 16 B inputs, C tier binary is 157 ms end-to-end versus 23,811 ms for the S-exp path. At that scale bend beats host hashlib by ~12×.
+The CUDA toolchain stays isolated to the leaf binary the worker spawns. No tier links libcudart; no tier requires nvcc at build time. Asm tier hosts workers through hand-written pipe2 + fork + execve syscalls.
bend runs on a 2-host LAN cluster today. The worker on each box is a lumbda C-tier process; daemons stay warm across requests. Round-robin selection lives in bend.lsp via *bend-workers* & the BEND_WORKERS environment variable.
bend runs on a 2-host LAN cluster. Round-robin selection lives in bend.lsp via *bend-workers* & the BEND_WORKERS environment variable.
| host | GPU | arch | port | daemons live | coexists with |
|---|---|---|---|---|---|
| host | GPU | arch | port | coexists with | |
3090-ai.foxhop.net | RTX 3090 (24 GB) | sm_86 | 9091 | shake / cgbn / secp / sim-ops-bin / sim-axis-flip | idle |
ai.foxhop.net | RTX 4090 (24 GB) | sm_89 | 9092 | shake / cgbn / secp | qwen LLM on GPU |
3090-ai.foxhop.net | RTX 3090 (24 GB) | sm_86 | 9091 | idle | |
ai.foxhop.net | RTX 4090 (24 GB) | sm_89 | 9092 | qwen LLM (llama.cpp) on GPU |
The 4090 box shares the GPU with a qwen LLM (llama.cpp). Our bend kernels fit alongside qwen comfortably because the secp256k1 / CGBN workloads burn the SMs only for milliseconds at a time, then release. The qwen server keeps its model weights resident; our kernels allocate transient VRAM for the per-call batch, run, free, return. 24 GB VRAM is enough for both.
- -Single-call kernel time at n=100k CGBN 256-bit mod-mul:
| host | kernel ms | wall ms (incl. PCIe + wire) | Mops/s (wall) |
|---|---|---|---|
| 3090-ai | 0.07–0.10 | 336 (median) | 0.30 |
| ai (4090) | 0.07–0.10 | 362 (median) | 0.28 |
At n=100k, kernels finish faster than the per-call PCIe transfer (6.4 MB tx) + LAN wire round trip. Both GPUs run the same workload in the same kernel time because neither saturates — both starve between calls. The 4090's raw FLOPS advantage shows up only when the kernel runs long enough to amortize wire overhead.
| workload | solo (1 host) | cluster (2 hosts) | speedup |
|---|---|---|---|
200 × n=1k CGBN mod-mul | 0.052 Mops/s | 0.084 Mops/s | 1.6× |
6 × n=100k CGBN mod-mul | 0.15 Mops/s | 0.18 Mops/s | 1.2× |
Speedup caps at 1.6× instead of 2× because the dispatching client serializes one call at a time. An async fan-out client unlocks the remaining 2× headroom. Workers themselves never block each other.
- -The first end-to-end run through the full lumbda → emit-ops-bin walker → bend → demo_ops pipeline landed today at runs/lumbda-sweep-001/. Two of six lever variants emitted & scored at p=11 point-add width:
| variant | n_ops | Σ Clifford | Σ Toffoli |
|---|---|---|---|
| Solinas + Fermat textbook B-Y | 48,763 | 1,687,232 | 749,056 |
| Solinas + refined B-Y (Phase B step 10) | 32,333 | 1,237,440 | 475,648 |
Refined Bernstein-Yang cuts Σ Toffoli by 36.5% at production-relevant width. Our small-fixture lever screen predicted −56% at p=5, & the p=251 ground-truth reference predicted −40%. Measured −36.5% sits within 3 percentage points of the larger-width prediction. The small-fixture lever screen earns its keep as a faithful predictor: sweep cheap at p=11, filter to winners, promote only winners to p=251 production cost.
Four remaining variants still emitting (the lumbda walker is CPU-bound on the local box at full Phase B width); dispatch-sweep.py auto-resumes against new .bin files as they land.
The binary handlers (handle-binary-shake, handle-binary-cgbn, handle-binary-secp) used to call delete-file unconditionally after daemon failure — if the daemon errored before writing the output portal, the missing-file raise crashed the entire listener. 12 guard lines across 6 sites ((if (file-exists? PATH) (delete-file PATH))) closed the gap. Fix held under sustained sweep traffic with zero crashes since deployment.
The 4090 box shares its GPU with a qwen LLM. Bend kernels fit alongside because secp256k1 / CGBN workloads burn SMs for milliseconds at a time then release; qwen keeps its weights resident, bend allocates transient VRAM per call. 24 GB VRAM holds both.
+Cluster aggregate (round-robin fan-out, sequential dispatcher): 1.6× at 200 × n=1k CGBN mod-mul, 1.2× at 6 × n=100k. Cap is client-side serialization; an async dispatcher unlocks the remaining 2× headroom. Workers themselves never block each other.
A form earns a slot here only after we have published a benchmark or measured one on our hardware. "I think this would be fast" does not earn a slot — the form-status column says planned until numbers exist.
cuda-clifford-stabilizer as originally scoped does not apply to our point-add circuit. Build agent measured Toffoli fraction 13.87% (well under the 40% threshold), then noticed the circuit contains no Hadamard or S gates — only X / CX / CCX / CZ / CCZ / SWAP / R / HMR / Z / NEG. State never leaves the computational basis. Aaronson-Gottesman tableau compression buys nothing when superposition does not exist; it reduces to exactly what sim_gpu.cu already does, at one bit per qubit per shot.
The cuda-sim-ops-bin 1.07× ceiling traces to memory-bandwidth on per-shot striped state, not algorithm choice. STABSim-class wins remain valid for QEC / surface-code workloads where H + S exist; that's a future workload, not point-add today.
Both replacement directions landed 2026-06-05; the bandwidth-bound diagnosis they were chasing turned out FALSE for our circuit.
-sim_gpu.cu — DONE (foxhop commit 1f7ac9d). 217 Mops/s @ K=32 M=4 on a 3090; 23.7× over per-shot N=4 at same M. Both kernels saturate at ~220–250 Mops/s. Axis flip's win is occupancy-amortization, not bandwidth redistribution. Right tool for lumbda's many-candidates × few-shots search-loop early-screen pattern.ops.bin packing (QECCOPS2) — DONE (foxhop commit 90484ca). 1.07× kernel speedup, 2.33× on-disk shrink (716 MB → 307 MB). The 3.5× projection assumed 56 B/op was VRAM-resident; ops_loader.c already narrowed to 28 B on load, so the realistic ceiling was 1.17×. Per-shot state traffic (qubits + bits per thread) dominates kernel bandwidth ~85× over the op stream.Both pivots converged on the same diagnosis: the 3090 is compute-saturated at ~250 Mops/s on the kickmix circuit, not bandwidth-saturated. Real next macro-lever: multi-GPU fan-out across our fleet.
-live — binary built, worker dispatches it, numbers recorded on our hardwaresurveyed — published benchmark cited, prototype binary not yet wrapped; speedup claims need verification on our fleet before promotion to liveplanned — design slot reserved, no binarysurveyed — published benchmark cited, prototype binary not yet wrappedThe catalog grows continuously. Each form below carries enough metadata for anyone to start a port: canonical reference, reported speedup, target hardware, sketch wire shape. Forms with HIGH relevance to our active missions (foxhop ECDSA work, undefect defect-scanning, unsandbox / unturf permacomputer infrastructure) move up the build queue.
| form | status | hardware | speedup vs CPU | wire shape | ||
|---|---|---|---|---|---|---|
| form | hardware | throughput | wire shape | |||
cuda-shake-fanout |
- live | RTX 3090 | -12× over host hashlib at 1 M × 16 B inputs | -(cuda-shake-fanout '(hex ...) out-bytes) + BSHK binary |
+ 12× host hashlib at 1 M × 16 B inputs | +(cuda-shake-fanout '(hex ...) out-bytes) + BSHK binary |
cuda-sim-ops-bin |
- live | RTX 3090 | -1.07× at 128 batches (8192 shots); crossover ~115 batches | +1.07× at 128 batches; crossover ~115 batches | (cuda-sim-ops-bin "path/to/ops.bin" n-batches) |
|
cuda-bignum-cgbn |
- live | +cuda-sim-axis-flip |
RTX 3090 | -1.28 Gops/s kernel mod-mul at n=1M (256-bit, ~256× GMP single-thread CPU); all 9 ops live (mod-add/sub/mul/sqr/inv/exp/reduce, add-no-mod, mul-no-mod-2x-width) | +217 Mops/s @ K=32 M=4 (many-candidates × few-shots) | +(cuda-sim-axis (variant-paths ...) n-shots) |
+
cuda-bignum-cgbn |
+ RTX 3090 | +1.28 Gops/s kernel mod-mul @ n=1M (256-bit, ~256× GMP CPU); 9 ops | BCGB binary: op_id + bitwidth + n + modulus + a + b |
|||
cuda-secp256k1-batched-mul |
- live | RTX 3090 | -v1 7.86 Mkeys/s @ n=1M; v3 (windowed-G w=4) 13.83 Mkeys/s @ n=1M — 1.76× v1, ~309× coincurve CPU. Day-4 v4 (v3 ladder + Montgomery batch inv) regressed -12% vs v3 due to v2's serial-per-block Phase B/D walks; warp-scan Phase B/D refactor needed before v4 wins. Daemon default now ships --window-w 4 |
+ 13.83 Mkeys/s @ n=1M (~309× coincurve CPU; windowed-G ladder w=4) | BSCP binary: scalars + base-point → BSCR points |
|
cuda-sim-axis-flip |
- live | -RTX 3090 | -217 Mops/s @ K=32 M=4 per-candidate-parallel kickmix sim; 23.7× over per-shot N=4 at same M; loses to per-shot by 14% at full N=128 saturation. Right tool for lumbda search-loop early-screen many-candidates × few-shots pattern | -(cuda-sim-axis (variant-paths ...) n-shots) |
-
cuda-secp256k1-batched-mul — batched secp256k1 scalar / point opsSpeedup: gECC 4.94× on unknown-point mul, 5.56× on ECDSA verify vs CPU. VanitySearch forks hit 6.5 Gkeys/s on RTX 4090, 8.6 Gkeys/s on RTX 5090, 2.65 Gkeys/s on RTX 3080. Endomorphism + Montgomery batch-inversion (one mod-inv per N points instead of N) carries the kernel.
+Reference numbers: gECC 4.94× on unknown-point mul, 5.56× on ECDSA verify vs CPU. VanitySearch forks hit 6.5 Gkeys/s on RTX 4090, 8.6 Gkeys/s on RTX 5090, 2.65 Gkeys/s on RTX 3080.
Wire: (secp-mul-batch (scalars . blob<N×32B>) (base-point . blob<64B>)) → (points . blob<N×64B>)
References: gECC paper · VanitySearch · VanitySearch-Bitcrack fork
+Refs: gECC paper · VanitySearch · VanitySearch-Bitcrack
cuda-bignum-cgbn — 256-bit modular arithmetic primitivesSpeedup: 100×+ on dense mul vs Xeon-20c + GMP + OpenMP on V100 (midsize-int study).
+Reference numbers: 100×+ on dense mul vs Xeon-20c + GMP + OpenMP on V100.
Wire: (cgbn-batch (op . mod-mul|mod-inv|mod-add) (modulus . blob<32B>) (a . blob<N×32B>) (b . blob<N×32B>)) → blob<N×32B>
References: NVlabs CGBN · midsize-int benchmarks
+Refs: NVlabs CGBN · midsize-int benchmarks
cuda-rho-pollard-walk — Pollard rho / kangaroo walksSpeedup: 87.7 M ops/sec on RTX 2070 Super for ECCp79 (Certicom challenge solved in ~3 hours). Original CUDA Pollard paper reports > 7.2 M points/sec at 256 threads on older HW.
+Reference numbers: 87.7 M ops/sec on RTX 2070 Super for ECCp79. Original CUDA Pollard paper reports > 7.2 M points/sec at 256 threads on older hardware.
Wire: (rho-walk-batch (start-points . blob<W×64B>) (steps . N) (distinguished-mask . blob<32B>)) → (distinguished . blob<K×96B>)
References: atlomak/CUDA-rho-pollard · oritwoen/kangaroo
+Refs: atlomak/CUDA-rho-pollard · oritwoen/kangaroo
cuda-clifford-stabilizer — tableau stabilizer simulator (Stim-on-GPU)Speedup: 186× over Stim (CPU SOTA) on equivalence-checking. STABSim a first GPU stabilizer sim to scale better than CPU on QEC workloads.
+Reference numbers: 186× over Stim (CPU SOTA) on equivalence-checking.
Wire: (stab-sim-batch (n-qubits . k) (circuit . blob) (n-shots . S)) → (samples . blob<S×ceil(k/8)>)
References: STABSim · Qimax · equivalence-checking
+Refs: STABSim · Qimax · equivalence-checking
cuda-bernstein-yang-inv — batched modular inverse (safegcd)Speedup: 3–10× per inversion over Fermat on CPU. No published dedicated CUDA implementation found — gECC uses Montgomery's batched-inversion trick instead. Standalone Bernstein-Yang-on-CUDA holds novel territory.
+Reference numbers: 3–10× per inversion over Fermat on CPU. No published dedicated CUDA implementation; Standalone Bernstein-Yang-on-CUDA holds novel territory.
Wire: (modinv-batch (modulus . blob<32B>) (xs . blob<N×32B>)) → blob<N×32B>
References: safegcd · Jumping for Bernstein-Yang
+Refs: safegcd · Jumping for Bernstein-Yang
cuda-ntt-poly — Number Theoretic TransformSpeedup: Up to 123× over CPU; 21× on RTX 3070; cuFFT-comparable kernel structure.
+Reference numbers: Up to 123× over CPU; 21× on RTX 3070; cuFFT-comparable kernel structure.
Wire: (ntt (mod . p) (omega . root) (xs . blob<N×8B>)) → blob<N×8B>
References: NTTSuite · FHE NTT
+cuda-radix-sort / cuda-prefix-scan — reduction primitivesSpeedup: 1.4 G keys/sec on Titan; 20–50× over CPU merge sort; 257× over Intel Xeon Phi for scan.
+Reference numbers: 1.4 G keys/sec on Titan; 20–50× over CPU merge sort; 257× over Intel Xeon Phi for scan.
Wire: (sort-u64 (xs . blob<N×8B>)) → blob<N×8B>
References: NVIDIA CUB · Onesweep
+Refs: NVIDIA CUB · Onesweep
-Sorted by reported speedup vs CPU descending. Speedups quoted from published benchmarks on the cited hardware; numbers labelled surveyed have not yet run on our fleet, so this table calls a paper a paper and a measurement a measurement.
Sorted by reported speedup descending.
| form | -speedup | -hardware | -relevance | -ref | -
|---|---|---|---|---|
| form | throughput | hardware | ref | |
cuda-minhash-weighted | 600–1000× vs numpy+MKL | Titan X vs 12-core Xeon E5-1650 | HIGH — undefect corpus dedup, CVE shard clustering | src-d/minhashcuda |
cuda-cuckoo-filter | 378× insert, 258× delete | A100 (TCF on Perlmutter) | HIGH — foxhop ECDSA candidate-pruning, undefect URL-seen filter | arXiv:2603.15486 |
cuda-aes-ctr-chacha20 | 211–400 GB/s (ChaCha8 / ChaCha20) | single GPU (RTX 3070 sustaining 672 Gbps Poly1305) | HIGH — AEAD on lumbda portal envelopes between tiers | AsyncGBP |
cuda-suffix-array-skew | 30–242× vs CPU SA-IS | Tesla K20 | MEDIUM — substring search for undefect source-corpus scans | Liu/Luo |
cuda-kdtree-build | 30–242× build, 1.6–200× kNN | RTX (RT cores) | MEDIUM — spatial index for unsandbox fleet locality | Zhou et al. |
cuda-sat-paraFROST-elim | 93× peak, 48× avg on variable elim | NVIDIA + CADICAL/Kissat baseline | HIGH — ECDSA / reversible-circuit equivalence checking via CNF | ParaFROST |
cuda-aho-corasick-pfac | ~50–100× (IDS pkt-inspect) | GTX-class | HIGH — secret/CVE-string scan across OSS source mirrors | PFAC |
cuda-dilithium-pqsig | 57.7× keygen+sign+verify vs single CPU thread | RTX 3090 Ti | HIGH — PQ migration for unsandbox TLS, foxhop disclosure signing | IACR 2024/1365 |
cuda-mc-options-pricing | 25–152× (barrier-call kernel 152×) | Tesla C1060 / modern | LOW — calibration form, well-understood arithmetic | GPU Gems Ch.45 |
cuda-cuFFT-batched-1D | 8–32× vs MKL; tcFFT 1.1–3.2× vs cuFFT | V100 / A100 | MEDIUM — spectrogram dispatch for punters-cc audio correlation | tcFFT |
cuda-blake3-tree | ~5–20× (tree mode) | Blaze-3 CUDA | HIGH — content-addressed lumbda portal frames, foxhop attachments | Blaze-3 |
cuda-bloom-filter-modern | ~6× CPU; 3.4 B inserts/s | B200 / Perlmutter | HIGH — foxhop candidate-pruning, undefect scan-target known-set | arXiv:2512.15595 |
cuda-gemm-batched-FP8 | 4.8× FP8 vs A100; 716 TFLOPS H100 | H100 SXM | LOW — calibration form, lattice-PQC matrix substrate | cuBLAS 12.0 |
cuda-batched-matrix-inverse | 4.3–16.8× vs MAGMA | P100 (650–800 GF SP) | LOW — linear-algebra verifiers on reversible-circuit checking | Superfri 2018 |
cuda-hash-join-radix | 4 B tuples/s single; 1.8 T tuples/s on 1024 A100 | A100 cluster | MEDIUM — undefect CVE↔commit↔package joins | ADMS-21 |
cuda-kmer-count | 4–6× vs KMC2; ~2× Jellyfish/KMC1 | RapidGKC, Gerbil | LOW — bioinformatics adjacency; identical bend-portal shape | RapidGKC |
cuda-cgraph-traversal | 38 B TEPS; PageRank half-billion nodes in seconds | DGX2 | MEDIUM — undefect dependency-DAG analytics, upstream call-graphs | cuGraph |
cuda-triangle-count-TRUST | ~1 T TEPS (first trillion-TEPS triangle counter) | multi-A100 | MEDIUM — community-structure detection for twitter-x-punters | TRUST |
cuda-ldpc-bp-decoder | 10 Gbps with early-termination | GPGPU | LOW — PQ-KEM noise modelling, SDR experiments on radio nodes | MDPI Electronics 2022 |
cuda-nvcomp-zstd | 2.2× decompress (zstd); 1.4× LZ4; 1.9× snappy | H100 / A100 | HIGH — undefect corpus shards, lumbda portal envelopes, permacomputer ingest | nvCOMP |
cuda-minhash-weighted | 600–1000× vs numpy+MKL | Titan X vs Xeon E5-1650 | src-d/minhashcuda | |
cuda-cuckoo-filter | 378× insert, 258× delete | A100 | arXiv:2603.15486 | |
cuda-aes-ctr-chacha20 | 211–400 GB/s | single GPU | AsyncGBP | |
cuda-suffix-array-skew | 30–242× vs CPU SA-IS | Tesla K20 | Liu/Luo | |
cuda-kdtree-build | 30–242× build, 1.6–200× kNN | RTX (RT cores) | Zhou et al. | |
cuda-sat-paraFROST-elim | 93× peak, 48× avg variable elim | NVIDIA + Kissat baseline | ParaFROST | |
cuda-aho-corasick-pfac | ~50–100× IDS pkt-inspect | GTX-class | PFAC | |
cuda-dilithium-pqsig | 57.7× keygen+sign+verify vs single CPU thread | RTX 3090 Ti | IACR 2024/1365 | |
cuda-mc-options-pricing | 25–152× | Tesla C1060 / modern | GPU Gems Ch.45 | |
cuda-cuFFT-batched-1D | 8–32× vs MKL; tcFFT 1.1–3.2× vs cuFFT | V100 / A100 | tcFFT | |
cuda-blake3-tree | ~5–20× tree mode | Blaze-3 CUDA | Blaze-3 | |
cuda-bloom-filter-modern | ~6× CPU; 3.4 B inserts/s | B200 / Perlmutter | arXiv:2512.15595 | |
cuda-gemm-batched-FP8 | 4.8× FP8 vs A100; 716 TFLOPS H100 | H100 SXM | cuBLAS 12.0 | |
cuda-batched-matrix-inverse | 4.3–16.8× vs MAGMA | P100 | Superfri 2018 | |
cuda-hash-join-radix | 4 B tuples/s single; 1.8 T tuples/s on 1024 A100 | A100 cluster | ADMS-21 | |
cuda-kmer-count | 4–6× vs KMC2 | RapidGKC, Gerbil | RapidGKC | |
cuda-cgraph-traversal | 38 B TEPS | DGX2 | cuGraph | |
cuda-triangle-count-TRUST | ~1 T TEPS | multi-A100 | TRUST | |
cuda-ldpc-bp-decoder | 10 Gbps with early-termination | GPGPU | MDPI Electronics 2022 | |
cuda-nvcomp-zstd | 2.2× zstd; 1.4× LZ4; 1.9× snappy | H100 / A100 | nvCOMP |
15 additional forms spanning ZK / SNARK provers, pairing crypto, tensor network contraction, sparse linear algebra, CV primitives, numerical solvers, generic belief propagation, MD/CFD kernels, convex optimization, DSP beyond cuFFT, DB aggregations, graph theory beyond triangle/PageRank. Sorted by reported speedup or absolute throughput descending.
+| form | -speedup / throughput | -hardware | -relevance | -ref | -
|---|---|---|---|---|
| form | throughput | hardware | ref | |
cuda-fluidx3d-lbm | 100–200× vs ANSYS Fluent / OpenFOAM; 8,799 MLUPS single A100 | A100 | unsandbox MEDIUM (HPC reproducibility, OpenCL backend matches our fleet) | FluidX3D |
cuda-mfcc-spectral | ~97× CPU MFCC; STFT ~75× via cuSignal vs SciPy | GTX 580 / RTX 30-series | unsandbox HIGH — punters-cc, BT-DISC forensics, real-time CC pipeline | cuSignal |
cuda-batched-lp-simplex | 95× over CPLEX; 5× over GLPK on a batch of 100K LPs | GTX 980-class | unsandbox HIGH — resource scheduling, Prime Mission workstation balancing | arXiv 1802.08557 |
cuda-betweenness-centrality-weighted | 30–150× warp-centric weighted BC | GTX onwards | undefect HIGH — workaholic-node detection on dependency DAG, directly matches MOAD-0001 model | arXiv 1701.05975 |
cuda-cudasift-orb-ransac | ~60× SIFT CPU→GPU (11 fps 1920×1440); 1.2 ms on GTX 1060; ORB 11.3× | GTX 1060+ | unsandbox MEDIUM (visual evidence pipeline for incident reports) | CudaSift |
cuda-cudasw-gasal2 | CUDASW++4.0 16.2× over v3.0; 134× over ADEPT; 5.71 TCUPS on H100; GASAL2 packing 750× vs NVBio | H100 (TCUPS) | undefect MEDIUM (binary-diff & patch-similarity at scale: SW reduces to opcode-sequence diff) | CUDASW++4.0 |
cuda-loopy-bp-mrf | 45× over CPU LBP for stereo MRF inference | GTX 280-class+ | undefect HIGH — LBP substrate for FuzzingBrain-style probabilistic program analysis | arXiv 2509.22337 |
cuda-sgm-stereo | 42 fps at 640×480 with 128 disparities on Tegra X1; 46 fps on discrete GPUs | Tegra X1 / discrete | unsandbox MEDIUM (embedded ARM+CUDA matches our edge node profile) | arXiv 1610.04121 |
cuda-hungarian-lap | 10–50× class; 400 M-variable LAP in ~13 s | NVIDIA GPU | unsandbox HIGH — workstation-to-queue balancing per Prime Mission; defect-cluster ↔ patch-bundle assignment for undefect | ScienceDirect |
cuda-msm-bls12-381 | 27.86× over Pippenger (RELIC) AVX baseline; 60% of Groth16 prover time on single GPU | A100 / RTX 4090 | ECDSA HIGH — Pippenger bucket sort + multi-G1 arithmetic shares branchless modmul shape with our reversible secp256k1 inner loop | SimdMSM TCHES |
cuda-pdwt-lifting | 15.9× over best optimized CPU DWT (lifting scheme) | GTX / Tesla | unsandbox MEDIUM (audio-IPC payload analysis, BT signal denoising) | PDWT |
cuda-tensornet-contract | 8–20× vs CuPy on contraction; tensor QR ~100× vs Xeon 8480+; tensor SVD ~10× | A100 | ECDSA HIGH — alternative to stabilizer/kickmix sim path; MPS/PEPS evaluates reversible secp256k1 circuits beyond Clifford | cuTensorNet |
cuda-ega-gpu-aggregation | 6.45–29.12× over CPU multi-pass EGA; group-by hash 19.4× | NVIDIA GPU | undefect HIGH — defect-corpus aggregation at planetary scale; unsandbox HIGH — telemetry queue aggregation | VLDB Top-k EGA |
cuda-bicgstab-ilu-spmv | SpTRSV 10.7×; ILU0 BiCGSTAB 3.2× vs cuSPARSE on MI210; GMRES(30) block-ISAI 1.4–6.9× | V100 / MI210 | ECDSA MEDIUM (sparse LA over GF(p) underpins lattice / index-calc); undefect MEDIUM (spectral analysis on DAG) | arXiv 2508.04917 |
cuda-icicle-snark-groth16 | ICICLE-Snark fastest Groth16 today; Mina GPU 3× over libsnark; NTT 91% of prover at large sizes | RTX 4090 / A100 | ECDSA MEDIUM (zk + MSM stack shares finite-field discipline); undefect MEDIUM (zk-prover defect scanning) | ICICLE-Snark |
cuda-fluidx3d-lbm | 100–200× vs ANSYS Fluent; 8,799 MLUPS single A100 | A100 | FluidX3D | |
cuda-mfcc-spectral | ~97× CPU MFCC; STFT ~75× via cuSignal | GTX 580 / RTX 30-series | cuSignal | |
cuda-batched-lp-simplex | 95× over CPLEX; 5× over GLPK | GTX 980-class | arXiv 1802.08557 | |
cuda-betweenness-centrality-weighted | 30–150× warp-centric weighted BC | GTX onwards | arXiv 1701.05975 | |
cuda-cudasift-orb-ransac | ~60× SIFT CPU→GPU; ORB 11.3× | GTX 1060+ | CudaSift | |
cuda-cudasw-gasal2 | CUDASW++4.0 16.2×; 5.71 TCUPS on H100 | H100 | CUDASW++4.0 | |
cuda-loopy-bp-mrf | 45× over CPU LBP for stereo MRF | GTX 280+ | arXiv 2509.22337 | |
cuda-sgm-stereo | 42 fps @ 640×480, 128 disparities | Tegra X1 / discrete | arXiv 1610.04121 | |
cuda-hungarian-lap | 10–50×; 400 M-variable LAP in ~13 s | NVIDIA GPU | ScienceDirect | |
cuda-msm-bls12-381 | 27.86× over Pippenger AVX baseline | A100 / RTX 4090 | SimdMSM TCHES | |
cuda-pdwt-lifting | 15.9× over best optimized CPU DWT | GTX / Tesla | PDWT | |
cuda-tensornet-contract | 8–20× vs CuPy; tensor QR ~100× vs Xeon | A100 | cuTensorNet | |
cuda-ega-gpu-aggregation | 6.45–29.12× multi-pass; group-by 19.4× | NVIDIA GPU | VLDB Top-k EGA | |
cuda-bicgstab-ilu-spmv | SpTRSV 10.7×; BiCGSTAB 3.2× vs cuSPARSE | V100 / MI210 | arXiv 2508.04917 | |
cuda-icicle-snark-groth16 | fastest Groth16 today; NTT 91% of prover | RTX 4090 / A100 | ICICLE-Snark |
Wave 3 filter-outs: AMGX algebraic multigrid (2–5×), GROMACS GPU (2–3×), NVOFA optical flow (7–10× borderline, dedicated hardware unit), Junction-tree BP per-message (0.68–9.18×), batched L-BFGS (134× single-case, not generalized). All below 10× or insufficiently general; revisit when shape changes.
- -A form is GPU-worth-it when at least one of:
cuda-sim-ops-bin shows ~5 s kernel overhead; only worth it past ~115 batches.When none of these hold, do not force the problem onto GPU. Find a different decomposition: parallelize on a different axis (per-candidate instead of per-shot), or stay on CPU & fan out across fleet hosts.
-cuda-secp256k1-batched-mul: biggest immediate win. VanitySearch's CUDA secp256k1 kernel hits 6.5 Gkeys/s on a 4090; bend gets a GPU-rate point-mul oracle for candidate validation.cuda-clifford-stabilizer: the right axis fix for our 1.07× cuda-sim-ops-bin ceiling. Reshape circuit-sim per-candidate-parallel; targets a Clifford fragment via STABSim-style tableau.cuda-bignum-cgbn: foundational layer. Generic 256-bit vocabulary lumbda calls without committing to a curve.Forms E, C, G follow once A–D give us measured numbers on our hardware. F & below revisit when our shape changes.
+When none of these hold, find a different decomposition: parallelize on a different axis, or stay on CPU & fan out across fleet hosts.
-examples/cuda-fanout/ — wire contract, daemon protocol, bench data, per-tier integration sketch.
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+examples/cuda-fanout/ — wire contract, daemon protocol, bench data, per-tier integration.
+CATALOG.md — canonical source for form metadata.