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bend Form D structural finding — pivot to axis-flip + ops.bin packing

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Form D build agent discovered: our point-add circuit contains no
Hadamard or S gates (only X/CX/CCX/CZ/CCZ/SWAP/R/HMR/Z/NEG).
State never leaves the computational basis. Aaronson-Gottesman
tableau compression buys nothing when superposition does not
exist; reduces to exactly what sim_gpu.cu already does at one
bit per qubit per shot.

Toffoli fraction measured 13.87% (well under the 40% threshold
the planner flagged). The 1.07x cuda-sim-ops-bin ceiling traces
to memory-bandwidth on per-shot striped state — not algorithm.

STABSim-class wins remain valid for QEC / surface-code work where
H + S exist; that's a future workload.

Two replacement directions queued:
  1. axis-flip sim_gpu.cu — per-candidate parallelism over per-shot.
     ~3 days. Reuses BSHK new op_id; no AG tableau.
  2. ops.bin packing — 56→16 B per op halves global-memory traffic.
     Addresses the actual bottleneck.

Catalog + public bend.html both updated. Form D progress doc at
examples/cuda-fanout/plans/form-D-build-progress.md documents the
structural reasoning in full.
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russell@unturf.com 2026-06-05 14:03:03 -04:00
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examples/cuda-fanout/CATALOG.md
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@ -174,6 +174,31 @@ aggregations, graph theory beyond triangle/PageRank.
- Junction-tree BP per-message: 0.68-9.18x — below threshold
- Batched L-BFGS: 134x reported but single mesh-size case, not generalized
## Form D structural finding — 2026-06-05
cuda-clifford-stabilizer does NOT apply to our point-add circuit.
Build agent measured Toffoli fraction 13.87% (well under 40%
threshold), THEN noticed the circuit contains no H or S gates —
only X/CX/CCX/CZ/CCZ/SWAP/R/HMR/Z/NEG. State never leaves the
computational basis. Stabilizer tableau compression buys nothing
when there's no superposition; AG reduces to exactly what
sim_gpu.cu already does, at one bit per qubit per shot.
The 1.07x cuda-sim-ops-bin ceiling traces to memory-bandwidth on
per-shot striped state, not algorithm. Two pivots under way:
- **axis-flip refactor of sim_gpu.cu** — per-candidate parallelism
over per-shot (Form D option 1). ~3 days.
- **ops.bin packing** — 56 -> 16 bytes per op halves global-memory
traffic; addresses the actual bandwidth bottleneck (Form D
option 3).
Form D as originally scoped (AG tableau for our circuit) is
**parked**. STABSim-class wins remain valid for QEC / surface-code
work where H + S exist; that's a future workload.
Progress doc: examples/cuda-fanout/plans/form-D-build-progress.md
## Build order — recommended 3-form runway
1. **A: `cuda-secp256k1-batched-mul`** — biggest immediate win. Drop VanitySearch's CUDA secp256k1 kernel as a BSHK worker; lumbda gets a 6.5 Gkeys/s point-mul oracle. Every candidate validation rides this form. Hardware already owned (3090 + 4090).