From 01a36f3fcde72fea9a2468a116783b1e8f11aa69 Mon Sep 17 00:00:00 2001
From: "russell@unturf.com" <russell@unturf.com>
Date: Fri, 5 Jun 2026 20:58:05 -0400
Subject: [PATCH] =?UTF-8?q?bend.html:=20drop=20false=20port=20claim=20?=
 =?UTF-8?q?=E2=80=94=20qwen=20runs=20on=20GPU,=20not=20on=20ports=209090/9?=
 =?UTF-8?q?091?=
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Earlier commit incorrectly named ports 9090+9091 as qwen LLM serving.
Agent's actual finding (ai.foxhop.net second-worker deployment) was
uid-992 Erlang Cowboy services on those ports — unsandbox infra,
not qwen. Qwen runs on the GPU itself, not on those TCP ports.

The coexistence story (our bend kernels share a 4090 with qwen
because we burn SMs for ms-at-a-time then release) stays intact;
the false port attribution removed.
---
 www/bend.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/www/bend.html b/www/bend.html
index 8268e29..b3a35ad 100644
--- a/www/bend.html
+++ b/www/bend.html
@@ -100,11 +100,11 @@ make gpu-worker LUMBDA=asm                # smallest footprint</code></pre>
   <thead><tr><th>host</th><th>GPU</th><th>arch</th><th>port</th><th>daemons live</th><th>coexists with</th></tr></thead>
   <tbody>
     <tr><td><code>3090-ai.foxhop.net</code></td><td>RTX 3090 (24 GB)</td><td>sm_86</td><td>9091</td><td>shake / cgbn / secp / sim-ops-bin / sim-axis-flip</td><td>idle</td></tr>
-    <tr><td><code>ai.foxhop.net</code></td><td>RTX 4090 (24 GB)</td><td>sm_89</td><td>9092</td><td>shake / cgbn / secp</td><td>qwen LLM serving on ports 9090 + 9091 (Erlang Cowboy, uid 992)</td></tr>
+    <tr><td><code>ai.foxhop.net</code></td><td>RTX 4090 (24 GB)</td><td>sm_89</td><td>9092</td><td>shake / cgbn / secp</td><td>qwen LLM on GPU</td></tr>
   </tbody>
 </table>
 
-<p>The 4090 box shares the GPU with a qwen LLM (vllm) serving on the same machine. Our bend kernels fit alongside qwen comfortably because the secp256k1 / CGBN workloads burn the SMs only for milliseconds at a time, then release. The qwen server keeps its model weights resident; our kernels allocate transient VRAM for the per-call batch, run, free, return. 24 GB VRAM is enough for both.</p>
+<p>The 4090 box shares the GPU with a qwen LLM (vllm). Our bend kernels fit alongside qwen comfortably because the secp256k1 / CGBN workloads burn the SMs only for milliseconds at a time, then release. The qwen server keeps its model weights resident; our kernels allocate transient VRAM for the per-call batch, run, free, return. 24 GB VRAM is enough for both.</p>
 
 <h3>Cross-GPU parity at small batches</h3>
 <p>Single-call kernel time at <code>n=100k</code> CGBN 256-bit mod-mul:</p>