undefect. CWE-407 — 63 sites patched across 27 ecosystems
Authors: russell@unturf.com · brackishbert@gmail.com · foxhop.net · TimeHexOn.com Patches, unit tests, benchmarks, whitepaper, and outreach briefs. Public domain — no copyright claimed. Use freely.
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package compiler.vectorapi;
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import compiler.lib.ir_framework.*;
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import java.util.Random;
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import jdk.incubator.vector.IntVector;
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import jdk.incubator.vector.LongVector;
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import jdk.incubator.vector.VectorMask;
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import jdk.incubator.vector.VectorOperators;
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import jdk.incubator.vector.VectorSpecies;
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import jdk.test.lib.Asserts;
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import jdk.test.lib.Utils;
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/**
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* @test
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* @bug 8287984
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* @key randomness
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* @library /test/lib /
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*asimd.*") | (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
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* @summary AArch64: [vector] Make all bits set vector sharable for match rules
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* @modules jdk.incubator.vector
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*
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* @run driver compiler.vectorapi.AllBitsSetVectorMatchRuleTest
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*/
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public class AllBitsSetVectorMatchRuleTest {
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private static final VectorSpecies<Integer> I_SPECIES = IntVector.SPECIES_MAX;
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private static final VectorSpecies<Long> L_SPECIES = LongVector.SPECIES_MAX;
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private static int LENGTH = 128;
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private static final Random RD = Utils.getRandomInstance();
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private static int[] ia;
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private static int[] ib;
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private static int[] ir;
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private static long[] la;
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private static long[] lb;
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private static long[] lr;
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private static boolean[] ma;
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private static boolean[] mb;
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private static boolean[] mc;
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private static boolean[] mr;
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static {
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ia = new int[LENGTH];
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ib = new int[LENGTH];
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ir = new int[LENGTH];
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la = new long[LENGTH];
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lb = new long[LENGTH];
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lr = new long[LENGTH];
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ma = new boolean[LENGTH];
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mb = new boolean[LENGTH];
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mc = new boolean[LENGTH];
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mr = new boolean[LENGTH];
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for (int i = 0; i < LENGTH; i++) {
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ia[i] = RD.nextInt(25);
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ib[i] = RD.nextInt(25);
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la[i] = RD.nextLong(25);
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lb[i] = RD.nextLong(25);
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ma[i] = RD.nextBoolean();
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mb[i] = RD.nextBoolean();
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mc[i] = RD.nextBoolean();
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.VAND_NOT_I, " >= 1" })
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public static void testAllBitsSetVector() {
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IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
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IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);
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av.not().lanewise(VectorOperators.AND_NOT, bv).intoArray(ir, 0);
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// Verify results
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for (int i = 0; i < I_SPECIES.length(); i++) {
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Asserts.assertEquals((~ia[i]) & (~ib[i]), ir[i]);
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.VAND_NOT_L, " >= 1" })
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public static void testVectorVAndNotL() {
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LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
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LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0);
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av.not().lanewise(VectorOperators.AND_NOT, bv).intoArray(lr, 0);
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// Verify results
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for (int i = 0; i < L_SPECIES.length(); i++) {
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Asserts.assertEquals((~la[i]) & (~lb[i]), lr[i]);
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
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@IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
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public static void testVectorVAndNotIMasked() {
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VectorMask<Integer> avm = VectorMask.fromArray(I_SPECIES, ma, 0);
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IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
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IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);
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av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(ir, 0);
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// Verify results
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for (int i = 0; i < I_SPECIES.length(); i++) {
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if (ma[i] == true) {
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Asserts.assertEquals((~ia[i]) & (~ib[i]), ir[i]);
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}
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
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@IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
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public static void testVectorVAndNotLMasked() {
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VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
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LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
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LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0);
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av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(lr, 0);
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// Verify results
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for (int i = 0; i < L_SPECIES.length(); i++) {
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if (ma[i] == true) {
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Asserts.assertEquals((~la[i]) & (~lb[i]), lr[i]);
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}
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.RISCV_VAND_NOTI_VX, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
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public static void testAllBitsSetVectorRegI() {
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IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
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int bs = ib[0];
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av.not().lanewise(VectorOperators.AND_NOT, bs).intoArray(ir, 0);
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// Verify results
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for (int i = 0; i < I_SPECIES.length(); i++) {
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Asserts.assertEquals((~ia[i]) & (~bs), ir[i]);
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.RISCV_VAND_NOTL_VX, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
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public static void testAllBitsSetVectorRegL() {
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LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
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long bs = lb[0];
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av.not().lanewise(VectorOperators.AND_NOT, bs).intoArray(lr, 0);
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// Verify results
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for (int i = 0; i < L_SPECIES.length(); i++) {
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Asserts.assertEquals((~la[i]) & (~bs), lr[i]);
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.RISCV_VAND_NOTI_VX_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
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public static void testAllBitsSetVectorRegIMask() {
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VectorMask<Integer> avm = VectorMask.fromArray(I_SPECIES, ma, 0);
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IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
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int bs = ib[0];
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av.not().lanewise(VectorOperators.AND_NOT, bs, avm).intoArray(ir, 0);
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// Verify results
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for (int i = 0; i < I_SPECIES.length(); i++) {
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if (ma[i] == true) {
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Asserts.assertEquals((~ia[i]) & (~bs), ir[i]);
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}
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.RISCV_VAND_NOTL_VX_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
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public static void testAllBitsSetVectorRegLMask() {
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VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
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LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
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long bs = lb[0];
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av.not().lanewise(VectorOperators.AND_NOT, bs, avm).intoArray(lr, 0);
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// Verify results
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for (int i = 0; i < L_SPECIES.length(); i++) {
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if (ma[i] == true) {
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Asserts.assertEquals((~la[i]) & (~bs), lr[i]);
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}
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}
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}
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@Test
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@Warmup(10000)
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@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"})
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@IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
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public static void testAllBitsSetMask() {
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VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
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VectorMask<Long> bvm = VectorMask.fromArray(L_SPECIES, mb, 0);
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VectorMask<Long> cvm = VectorMask.fromArray(L_SPECIES, mc, 0);
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avm.andNot(bvm).andNot(cvm).intoArray(mr, 0);
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// Verify results
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for (int i = 0; i < L_SPECIES.length(); i++) {
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Asserts.assertEquals((ma[i] & (!mb[i])) & (!mc[i]), mr[i]);
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}
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}
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public static void main(String[] args) {
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TestFramework.runWithFlags("--add-modules=jdk.incubator.vector");
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}
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}
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